Show HN: Naja-Verilog – Structural Verilog Parser(github.com)
github.com
Show HN: Naja-Verilog – Structural Verilog Parser
https://github.com/xtofalex/naja-verilog
3 comments
Thanks for the feedback sacheendra.
You are right about the lack of documentation, starting with a proper README, definitely on the top of the TODO list.
Still working on testing the structural Verilog language support, then will soon focus on documentation.
If there are developers around willing to early test structural verilog support or Naja: C++ netlist data structure, don't hesitate to contact me.
One thing to note: Naja-Verilog and Naja interact but are not tied: Naja structural verilog parser can be used to build any data structure or in any project needing structural verilog support (Yosys or Vivado synthesis outputs for instance).
Hi again, I've updated the README with a minimal set of informations. I hope this clarifies the purpose of the project. I'll later work on the detailed API documentation.
All feedbacks are welcomed.
The linked repo doesn't have an informative Readme. An example showing showing Naja differs from existing tools would help people unfamiliar with Electronic Design Automation, like me.