Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC(github.com)
github.com
Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
https://github.com/stnolting/neoTRNG
It is based on phase noise, consumes less than 60 LUT4s/FFs and achieves up to 7.99 bits of entropy per byte. Feel free to comment if you have any questions, ideas or thoughts :)
3 comments
This is pretty neat! I think it's worth doing more analysis on the entropy cells separately from the entropy extractor. For example, the von Neumann extractor requires exchangeability of the input bits. Does this hold? In the setting where there is no phase noise from the entropy cells (and hence no entropy), does the TRNG give any output? Assuming some basic model (maybe measure this?) about gate delays, how much entropy should be generated by each entropy cell?
It's worth putting an asterisk next to this that the theory of operation isn't terribly robust. Yes, phase noise is a valid way to sample thermal noise (a true random source) but it's not clear that this is what you're actually measuring on any given implementation of the TRNG. Depending on the synthesis and PnR of this module in your larger design, there's a good chance you'll have a correlation which some other part of your design especially as density goes through the roof. While it's likely to still pass statistical tests and seem chaotic, it might not be an actual TRNG without you putting in a lot of work to isolate it.
I have a lattICE fpga (the usb stick) and 2 older (at least 13 years) xilinx fpgas, are these too slow for this? I don't have any toolchains installed, so i'd appreciate knowing what i am getting in to before breaking out any of the FPGAs