Solo ASIC tapeout on a budget: detailed write up(essenceia.github.io)
essenceia.github.io
Solo ASIC tapeout on a budget: detailed write up
https://essenceia.github.io/projects/blake2s_hashing_accelerator_a_solo_tapeout_journey/
13 comments
Might as well just link directly to the blog post: https://essenceia.github.io/projects/blake2s_hashing_acceler...
Good suggestion, fell free to post it since you have more karma.
I know he jokes that running a marathon is theoretically possible with running shoes, it really isn't too hard though with programs like Couch to 5km https://c25k.com/. Multiple members of family have run marathons from as little as 6 months from nothing.
This is very interesting, for someone not involved in doing chip design, it's very interesting to get an idea of the open source landscape. Very exiting. I like the idea of consolidating some power electronics and logic into a single chip at some point, for example a BLDC driver with embedded MOSFETs, gate drivers and MCU. But this is a pipe dream for now. But I know it's possible.
I already see single-chip battery chargers (admittedly a lot simpler) that do both the charging logic (constant current until setpoint, then constant voltage until current drops below configured threshold).
A lot of stuff could be consolidated into single chips, making PCBs smaller and simplyfing designs.
I already see single-chip battery chargers (admittedly a lot simpler) that do both the charging logic (constant current until setpoint, then constant voltage until current drops below configured threshold).
A lot of stuff could be consolidated into single chips, making PCBs smaller and simplyfing designs.
The issue with consolidating a BLDC driver is thermals more than anything else, right? Much easier to keep the MOSFETs cool if they aren't packed in on chip. Plus you can customize their size to the load.
Yeah, for most applications it's preferred that way. It's only for the ultra-compact, ultra high volume production, ultra high energy densities that packing it all into a single, unobody die and package could make sense. It would offer minor benefits anyway. Only when every gram, watt and mm3 counts would it be worth even thinking about. Maybe for very large vehicles (trucks, boats) or extremely small applications it would make more sense?
See also Luke Wren's Mastodon thread on taping out a RISC-V chip in two weeks: https://types.pl/@wren6991/115572086565318699
It is a bit misleading to say 'Solo', when TinyTapeout is involved.
Still clearly effortful work, though. I don't want to disparage it.
Still clearly effortful work, though. I don't want to disparage it.
RP2040 is not new. A bit odd to say it is. I then thought maybe this was from a few years ago, but it's not, so idk
Very cool but I stopped reading when I realized that the blog post was written by an LLM.
> These weren’t just inconveniences; they fundamentally shaped the architecture, capping performance more than any internal logic constraints.
This sentence sealed the deal for me but I was already suspicious for the preceeding sections.
> These weren’t just inconveniences; they fundamentally shaped the architecture, capping performance more than any internal logic constraints.
This sentence sealed the deal for me but I was already suspicious for the preceeding sections.
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I keep subconsciously dismissing TinyTapeout because the time horizon is so long and I don't have a cool project idea that requires an ASIC, but it's probably a really good idea to do uncool things that don't require ASICs, to become familiar with the process and be able to do cool things later eventually. (Libre Hardware phone, anyone?)