Why refactor the code?: less repetition, clearer intent, easier to change timing/logic by editing a table instead of code paths.
Feedback welcome—especially ideas to extend it.
(This post is part of Resorte, a Spanish magazine (comics, hobbies, technical notes) inspired by Argentina’s legendary Lúpin. If you read Spanish, check it out.)
All the sources for the designs and testbenches were tested on Vivado and are available at GitHub. For the generic implementations I used unconstrained ports, which gives much simpler and compact code than using generic parameters.
The implementation of the round-robin arbiter uses a very clever and (again) compact algorithm.
Honey and lemon juice, mildly hot (put water in a pot, and the honey and lemon juice in a smaller glass inside the pot, stir until it is liquid and mildly hot).
Grandma recipe, works for me.
Not a medical advice
For me, one option is to be able to learn processors in depth. You want to understand how one works? You can always emulate it in SW, but on an FPGA you can make them interact with the real world in real time and probe them at the same time, with ready made signal analyzers that the vendors provide, and/or by making your own tools.
Another option, do you want to see by yourself how caching improves code performance? You can make that on an FPGA also.
I have done some time ago a very nice course which is called From Nand to Tetris, that teaches how to go all the way from gates to a processor. My plan for the near future is to implement the NAND2Tetris processor on a Basys 3 board, and make some of the examples I mentioned (like, probing internal registers using HW tools, or seeing by yourself how a cache improves performance). I hope to make some of these things available on my site. I am the OP, but just in case, my website is https://fpgaer.tech
Following Altera acquisition by Intel, and Xilinx acquisition by AMD, perspectives for many FPGA designers were gloom. There was a general feeling that the two biggies would go to a road where the FPGA is only and add-on or coprocessor for CPU workhorses, for applications like Data centers and ML acceleration.
Well, according to these news from Intel, that's not the case. Intle announces new mid-level FPGAs and even new FPGA to compete with Xilinx RFSoCs
That it why it was so much a joy to buy magazines. Those magazines with their program listings, the adds, the letters. I remember to this day when I was with my girlfriend for a long time typing long listing of POKEs to hear music from the magnificent SID.
I know it is not directly related to this magazine, but this nostalgia brought back to me the name of my favorite magazine those days: Ahoy!
And of course, who can forget the wonderful adds for the games from Infocom (Zork et al), who would "stick their graphics where the sun don't shine!". They were text based games, and very succesful on those days
Hi, I am a professional FPGA designer. I used to be a board designer many years ago, and most of the time I used the tools from Mentor Graphics. Only when I worked for a startup I used Orcad who, compared to Mentor Graphics, was really in another (much lower) league. The differences between Mentor Graphics and Orcad (15 years ago, when I was still a board designer) were many: Processing speed, integration between schematics entry, constraint management and layout tools, etc.
The problem is nice but the solution proposed at the website is too convoluted. The straight solution is simple. The mid door must say the truth, so left and right doors must lie. Taking these three simple facts into account, the exit is on the right door.
Feedback welcome—especially ideas to extend it.
(This post is part of Resorte, a Spanish magazine (comics, hobbies, technical notes) inspired by Argentina’s legendary Lúpin. If you read Spanish, check it out.)