Maybe, or maybe the size of the chair market grows because with $2 chairs more buyers enter. The high end is roughly unaffected because they were never going to buy a low end chair.
I guess we’re being a bit vague on timeframe but chrome books launched in 2011 so they’re one of those products that took ~10 years to be an overnight success, with 2020 being an accelerant. So my vote is no.
I posted this example before but academic papers on algorithms often have pseudo code but no actual code.
I thought it would be handy to use AI to make the code from the paper so a few months ago I tried to use Claude (not GPT, because I only have access to Claude) to recreate C++ code to implement the algorithms in this paper as practice for me in LLM use and it didn’t go well.
The largest plant in the world is the Three Gorges Dam in China at 22GW and it’s off the scales huge. We’re not building the equivalent of four of those every year.
Unless the plan is to power it off Sam Altman’s hot air. That could work. :)
Cost per transistor is increasing. or flat, if you stay on a legacy node. They pretty much squeezed all the cost out of 28nm that can be had, and it’s the cheapest per transistor.
“based on the graph presented by Milind Shah from Google at the industry tradeshow IEDM, the cost of 100 million transistors normalized to 28nm is actually flat or even increasing.”
I’m with you, I’m not sure the volume or cost would be less once you factor in capacitors that are high enough quality for the application.
The datasheet mentions low profile a lot. That does make sense as one can make a flat, high quality, capacitor. Making a flat high quality inductor is harder and probably more expensive and likely consumes more volume overall. I can imagine some applications where being flat is important, like the back of a panel.
These types of switching circuits are very common inside ASIC where the high speed isn’t an issue, you don’t need to move all that much charge, and one can’t easily (if at all) support inductors.
For some definitions of serious, sure. The main critical piece that’s missing is all the testing infrastructure. Buying 100 or so ASICs for university use is one thing. Buying 100K, or more, is another.
Not the gdb support via jtag that software engineers need, they have that. But the various manufacturing test suites, which do modify gate netlists, and automated circuit characterization techniques that electrical engineers and the manufacturing engineers use.
But the magic is in the “find patterns” stuff as memorization is just data storage. If you think of the machine learning algorithms as assigning items a point in a space, then it does uncover neighbors, sometimes ones we might not expect, and that’s interesting for sure.
But I’m not sure it’s analogous to what people do when they uncover patterns.
That’s interesting because I can’t imagine learning a subject without a textbook. I have a hard time believing another medium would have the depth and density to get all the points across. Although it does depend on the subject matter and one’s learning goals.
But I also do read textbooks for fun… Now that I have a few decades of experience in a lot of these subjects I get way more out of the books. And I can start to understand more of the meta information. Like, of all the things the author could’ve used as an example, why did they pick that. Also, it’s hugely interesting for me to look at the homework problems and theorize why this particular problem was picked. Especially fun for electrical engineering books. But ya, I’m weird like that.
Isn’t the primary issue that newer designers don’t know they show run ERC (or that ERC even exists)? Isn’t your tool going to have the same issue? i.e. how do user even know they should run it in the first place? How do you plan to overcome that barrier?
I’m not against more automated checkers, I’m very much for automated checkers, but I’m curious how you plan to not repeat the mistakes of the past.
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