The simplest processors use one clock per instruction with a Harvard architecture. This allows their control unit to be a combinational circuit instead of a Finite State Machine (and depending on how your memories work you might even avoid having an instruction register).
Most one-instruction processors take multiple clocks and often need extra registers (for fetching 16 bit addresses from an 8 bit wide memory, for example) [1].
The four instruction MCPU [2] is not as bad to program as the one-instruction computers (it still needs 10 times as many instructions as a RISC-V, for example) while being very simple. Making it Harvard allows it to be slightly simpler and making it 16 bits allows it to run non trivial programs [3].
I think there were actually 68000 transistor positions. In the ROMs and PLAs not every potential transistor is populated but the missing ones were counted as well. But the number of actual transistors is only slightly smaller so it doesn't really matter.
One chip that could be used as a memory mapper for the 9900 (but wasn't in the TI99/4A) was the 74LS670, which was used in the IBM 5150 PC to allow the 8237 DMA chip to access more than 64KB (a limit that wasn't a problem when used in a 8080 system).
Note that RISC5 [1], a project created as a target for Wirth's Oberon compilers, is a different project from RISC-V [2], a project created at Berkeley which became what is currently the most popular open source ISA.
We were stuck with 33MHz PCBs for a long time as people kept trying and failing to get 50MHz PCBs to work. Then Intel came out with the 486DX2 which allowed you to run a 50MHz processor with an external 25MHz bus (so a 25MHz PCB) and we started moving forward again, though we did eventually get PCBs to go much faster as well.
The Transputers (mentioned in other comments) had already decoupled the core speed from the bus speed and Chuck Moore got a patent for doing this in his second Forth processor[1], which patent trolls later used to extract money from Intel and others (a little of which went to Chuck and allowed him to design a few more generations of Forth processors).
The naming of processor sizes is the subject of debate. I call a "pure 8 bit processor" one that has 8 bits for both data and addresses. Like the Kenbak-1. But these are so rare and educational rather than practical that it is very reasonable to call hybrid 8 bit / 16 bit processors just "8 bit".
This use of sloppy terms shouldn't make us forget that they are using an address extension trick, just like all those 16 bit processors that wanted to go beyond 64KB (for byte addressed such as the PDP-11, Z8000 or 8086) or 128KB (for word addressed, like the Xerox Alto's modified Data General Nova model).
Michael J. Flynn, best known in the computing world for his taxonomy of parallel computing (SISD, SIMD, MISD and MIMD), passed away on December 24, 2025
Most people are not aware that after the failure of the PS/2 attempt to control the PC market, IBM tried a third time using 7 patents it had for the PC AT (they didn't have any on the original PC or the XT). In the first half of the 1990s they went after the chipset makers (mostly in Japan at that time) and in the second half of the 1990s they went after the PC makers themselves all around the world. The would threaten to sue for all machines made up to that point unless they licensed not only the 7 AT patents (which would expire in 2001) but also a bunch of other unrelated patents that were much newer. As far as I know everybody signed the deal, which meant that IBM could make money without actually making any PCs themselves.
One issue he mentioned is still true today in Brazil's universities: while in theory you can ask to transfer from one course to another, in practice you have to drop out of your current school and take the entrance exam for the other one. And then you waste a lot of time trying to get your grades for the courses you have already taken recognized as equivalent so you don't have to start from scratch.
For him to move from math to electrical engineering to physics in Brazil would mean going through this twice. This might make him take some 7 or 8 years to graduate.
I guess this inflexibility makes things easier for the administrators. They know they will have 25 students in the statistics class in 2028 and so know how many teachers to hire to handle that.
Actually, the 68000 had one full (all operations) 16 bit ALU and two more simple (add/subtract, so AU might be a better name) 16 bit ALUs so in the best case it could crunch 48 bits per clock cycle. The 8086 had one full 16 bit ALU and one simple 16 bit ALU (the ancestor of todays AGUs - address generator units).
The 68000 actually had both microcode and nanocode, so it was even further from hardwired control logic than the 8086. In terms of performance the 68000 was slightly faster than the 286 and way faster than the 8088 (I never used an 8086 machine).
The Indy 500 was actually part of the official Formula 1 calendar from 1950 to 1960, though the two series diverged after that.
Some Indy features (refueling, changing tires even if they didn't have a puncture, safety cars) got adopted by F1 through the 1980s, specially as F1 started to lose audience to the American series in the early 1990s.
Though a problem, as you point out, it still happened. The 6800 based SWTPC was followed by 6809 machines what need to have all their software reassembled.
On the other side of the cpu wars, all those 8080 machines moving on the Z80s got to keep all their binary software, which happened again for IBM PCs and clones as those evolved.
My own memory of the events (which might be very wrong) was that a new vice-president of IBM semiconductors decided to drop bulk CMOS and focus exclusively on SOI (Silicon On Insulator). That suddenly left Transmeta without chips to sell. They had to scramble to find a new supplier and design their next generation processor for it (since the Crusoe wasn't portable to any other fabs). They were able to launch their Efficeon on TSMC 130nm (with a later version on Fujitsu 90nm) but the gap in supply was far worse for a startup than it would have been for a big company.
The VM in Slang had been previously published as part of the "blue book" (now that is what I call open source!) some 14 years before, and as the paper you linked to mentioned, Mario Wolczko at the University of Manchester had typed it in so it was available in machine readable form.
They did drop the object memory part completely and designed a new one from scratch.
Previously people had manually translated the VM from Slang to Pascal or C (I did so myself in 1986) but for this project they wrote a tool for that (in Smalltalk, of course).
Here is another copy of the "Back to the Future" paper:
Most one-instruction processors take multiple clocks and often need extra registers (for fetching 16 bit addresses from an 8 bit wide memory, for example) [1].
The four instruction MCPU [2] is not as bad to program as the one-instruction computers (it still needs 10 times as many instructions as a RISC-V, for example) while being very simple. Making it Harvard allows it to be slightly simpler and making it 16 bits allows it to run non trivial programs [3].
[1] https://github.com/jeceljr/SBN/blob/master/sbn.pdf
[2] https://github.com/cpldcpu/MCPU
[3] https://github.com/jeceljr/digitalCPUzoo/tree/main/MCPU