TSMC: SoIC(3dfabric.tsmc.com)
3dfabric.tsmc.com
TSMC: SoIC
https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm
24 comments
Is there a risk in one manufacturer seemingly getting so far ahead in terms of being able to deliver high-performance processors?
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What would the alternative be?
Slowing all progress down so everyone can keep up?
Slowing all progress down so everyone can keep up?
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I assume keeping the parts cool becomes a big issue. You get twice the amount of heat to dissipate within the same area. Or is there some workaround?
The work around would be microfluidic coolers, which aren't production ready yet, I believe.
No Workaround AFAIK, the idea right now is not to stack compute die on top of each other but other things like SRAM or parts that uses little energy for both cost and space efficiency.
The goals here are kind of sideways from heat dissipation.
* Different parts from different processes — for example DRAM and CPU need different processes, so it doesn't work to put them on the same chip — this integration is a step closer than on-package.
* Yield — if you really want sixteen cores, and you're pushing the edge of your process, your yield for perfect eight-core chiplets will be dramatically better than for a sixteen-core chip or chiplet.
But yeah concentrating all that into multi-chip chip will also concentrate the heat.
* Different parts from different processes — for example DRAM and CPU need different processes, so it doesn't work to put them on the same chip — this integration is a step closer than on-package.
* Yield — if you really want sixteen cores, and you're pushing the edge of your process, your yield for perfect eight-core chiplets will be dramatically better than for a sixteen-core chip or chiplet.
But yeah concentrating all that into multi-chip chip will also concentrate the heat.
It is like national security matter and relatively inexpensive when talking about nation's budget scale. Why countries don't make their own chips? Should this be in the realm of public companies just like healthcare or energy in some countries?
Whoa! Blew through my marketing gibberish budget less than one paragraph in.
I wish all this technology were more accesible. but they gotta protect their trade secrets (I guess...).
I've heard about something called 'dycryl process' (in chip photolitography) but it is not the kind of info that it's easily found, nor easily understood even if I could google for it.
I've heard about something called 'dycryl process' (in chip photolitography) but it is not the kind of info that it's easily found, nor easily understood even if I could google for it.
They could give you all the recipes and steps, but a newcomer isn't going to make it due to the needed experience and expertise.
>I wish all this technology were more accesible. but they gotta protect their trade secrets (I guess...).
open source their manufacturing process? everyone can get EUV machine and all the components to make chip. you figure out the better yield part or packaging like TSMC
open source their manufacturing process? everyone can get EUV machine and all the components to make chip. you figure out the better yield part or packaging like TSMC
Whats, Whys and Hows of TXMS-SoIC : https://3dfabric.tsmc.com/english/dedicatedFoundry/technolog...
Papers :
* https://ieeexplore.ieee.org/document/8811194
* https://ieeexplore.ieee.org/document/8776486
Papers :
* https://ieeexplore.ieee.org/document/8811194
* https://ieeexplore.ieee.org/document/8776486
Too bad they chose a name already taken by another very well established IC packaging technology : https://en.wikipedia.org/wiki/Small_outline_integrated_circu...
SOIC is the external package though, not sure it'll be that confusing as many chips are typically packaged in many different packages.
Could this be used for the next generation of HBM?
Here is a good diagram (sans the silicon interposer): https://www.researchgate.net/figure/3D-stacked-DRAM-example-...
Btw, memory has been stacked like that for a decade or more. Used to be stacked + wirebonded. But now, we have through-silicon vias (TSVs). The reason you can stack memory like that are many, one of them being thermals / power density.
[1] https://www.youtube.com/watch?v=t6KUnC-oU5g