The main reason is just due to me knowing my own limitations. SRAM is really simple to interface with and i've not yet tried to write a DRAM controller since its much more complex. Putting SRAM on the board made me more confident about the project. I did have it in mind that I could try to use the DRAM in place of the SRAM at a later stage (as you suggest) as a good way to focus on learning how to use it.
Thats an oversight on my part, I should put a license on it. I would love for anyone to be able to build one or tinker with the code as they want to. After all I was only able to make this because others shared their projects that I could learn from.
The bus controller was fairly straight forward. I found the timing diagrams in the V20 datasheet to be pretty easy to follow. The clock for the CPU is generated by the FPGA which I derived from a clock running at twice the speed, that made it easy to pick which clock edges I wanted to sample from or assert data for the CPU on. I did have a bug or two in there early on which meant that memory writes would not store the data I was expecting as I sampled the data bus at the wrong time. That was a tricky one as the bug would only become visible when that location was loaded from again. The CPU i'm using is rated for 16Mhz, but i've only tried to push it up to 10Mhz so far so I have a bit of margin. Some more issues might pop up if I push the speed higher I suspect. Its very stable as it is now and i've not seen any issues I could attribute to the bus handling.