Many professional books these days have issues with registration, bleed, trimming, etc. The quality is quite poor, to the point where I have fatigue determining if a book is "legit" or not.
How awesome would it have been to be a high performing student, writing programs that a lower performing student would have to execute manually on your simulated computer system. So much good stuff here. Do you want to layout the nand gate or BE the nand gate? Or be the one that decides which problems the nand gate solves?
There are lots of other FPGAs that are still available for RISC-V to target that are precluded from this announcement.
ARM used to sue anyone trying to make an ARM clone and now this. Great news for RISC-V. At least one if not two low end FPGA manufacturers will be shipping a fabric with hard blocks supporting RISC-V.
I think it is a great short and long term move. The new smaller processes aren't getting us to faster clock rates, they are making things cheaper. GF can get to the same point by optimizing their current processes.
If your macro isn't changing execution semantics, it probably doesn't need to be a macro.
This is why (if needs to be a special form if your language is eager, but you want to have short circuit conditionals. If you language is lazy, lots of things DON'T need to be macros.