I want to mention another awesome project, which implements PDP-11 on FPGA and can be used with PiDP-11 panel. (PiDP-11 by default uses software emulator running on Raspberry Pi.)
Not the parent poster, but my experience may be relevant.
My background is exclusively in software engineering and computer science. I started by reading “Digital Design and Computer Architecture”. There’s new RISC-V edition https://a.co/d/imzGBK5 as well as freely available ARM edition https://dl.acm.org/doi/book/10.5555/2815529. The book starts from Boolean logic and transistor technology and goes all the way to assembly programming with everything in between. Most importantly gives great introduction to HDLs. Next I played with a bunch of hardware projects specifically targeting inexpensive Arty-A7 board to get comfortable with FPGA tooling.
I can attest to the parent saying that this is sufficiently different from software engineering I do at my day job and therefore feels a lot more like hobby. Especially if you also foray into wire-wrap prototyping, PCB design and assembly. Finding and fixing analog "bugs" is so much fun!
I started by reading “Digital Design and Computer Architecture”. There’s new RISC-V edition https://a.co/d/imzGBK5. The book starts from Boolean logic and transistor technology and goes all the way to assembly programming with everything in between. Most importantly gives great introduction to HDLs. Next I played with a bunch of hardware projects specifically targeting inexpensive Arty-A7 board to get comfortable with FPGA tooling.
It has TTL RGBI and composite NTSC outputs. The latter is actually very interesting in that it can produce 16-color images using color smearing effect on NTSC TV. Many games from the period used this to achieve more colorful graphics at the expense of dropping to 160x200 resolution. OP port of Wolf3d is also supporting this mode.
I am working on FPGA-based converter to be able to show RGBI and composite CGA on modern VGA screens.
Yes, specifically IBM PCjr-ish clone. Compared to IBM PC 5150 it has 2x slower access to the first 96K of RAM due to “integrated” nature of its non-standard take on CGA. But, the rest of RAM is actually faster than IBM PC because it is a modern retro computing extension card made with fast SRAM.
This two-part blog explains step by step how to build a robot starting from training the ML model, using FPGA for hardware acceleration, writing an embedded C program and finally assembling everything on the chassis.
We work on an open source tensor processing unit at https://tensil.ai. It is not RISC-V based since only a handful of very simple instructions is needed for expressing data flows typical in ML.
Something like the Alveo PCIe card has onboard HBM/DDR4 memory large enough for Tensil DRAM pools, so this would be similar to how GPU operates but could also reach to host memory via PICe if needed. Embedded applications with Zynq 7 and UltraScale+ have ARM processors on the same chip with FPGA and (usually) DDR as separate chips on one PCB. In this case, Tensil DRAM pools are just contiguous memory blocks in the memory shared with the CPU. We will be publishing documentation on the compiler design soon--stay tuned!
Great questions! With Tensil, all computations are performed on the FPGA. In addition to matrix multiplication Tensil supports SIMD instruction with various operations. The ML activations, average and maximum pooling, normalization, and image resizing use SIMD instruction. Some ML operations, such as padding, are achieved by changing the memory layout. Tensil uses DRAM0 and DRAM1 memory pools (usually in DDR memory) to interact with the host to read model inputs and weights and write outputs. It also uses these pools to offload intermediate results between layers and between tiles within a layer when FPGA does not have sufficient BRAM, which is common on lower-end devices. Tensil compiler takes care of finding the most efficient memory scheduling for given on-FPGA memory size.
Very glad to see Rust on PIC32! This microcontroller is one of the very few that is still made in DIP package making it ideal for breadboardind and easy through-hole soldering, and by far most powerful, making it ideal choice for interesting projects.
Hello HN. SIDfi is a single-board self-contained SID file player. SIDfi requires the original MOS 6581 chip or a pin-compatible replacement such as ARMSID. SIDfi plays tune files such as High Voltage SID Collection from a FAT-formatted memory card and displays current tune information on a small LCD screen. Buttons on the LCD screen can be used to control the playback.
SIDfi is still very much work in progress. I am planning to add ability to play specific SID tunes and directories with joystick buttons and improving playback screen presentation.
Shoreline was founded to reduce operational pain. We have experience building and operating mission critical databases, cloud services with millions of hosts, and self tuning feedback control systems. We want to reduce tickets and improve availability by an order of magnitude through automation. We are well funded and based in Redwood City, California and Iasi, Romania.
Have you designed, built, and operated distributed systems? Love correctness, fault tolerance, and scalability? Shoreline is hiring distributed systems engineers to build our core product: a programmable & distributed control plane designed for scalability, fault tolerance, and portability.
What you'll be doing
- Implementing a distributed control plane in Elixir / Erlang and verifying, formally and through tests, to guarantee correctness and fault tolerance.
- Defining the semantics of the distributed ops language and implementing the distributed runtime.
- Designing & implementing a distributed event recognition and signalling system.
- Designing & implementing a distributed metrics subsystem and feedback control algorithms for distributed control.
- Build systems with arbitrary scale in mind e.g. millions of nodes.
You'll use standard software development best practices such as version control and participate in software development processes such as code and design reviews.
We pay competitively. While this position can be remote, you may be asked from time to time to travel to and work from the main office located in Redwood City, CA.
Shoreline was founded to reduce operational pain. We have experience building and operating mission critical databases, cloud services with millions of hosts, and self tuning feedback control systems. We want to reduce tickets and improve availability by an order of magnitude through automation. We are well funded and based in Redwood City, California and Iasi, Romania.
Have you designed, built, and operated distributed systems? Love correctness, fault tolerance, and scalability? Shoreline is hiring distributed systems engineers to build our core product: a programmable & distributed control plane designed for scalability, fault tolerance, and portability.
What you'll be doing
- Implementing a distributed control plane in Elixir / Erlang and verifying, formally and through tests, to guarantee correctness and fault tolerance.
- Defining the semantics of the distributed ops language and implementing the distributed runtime.
- Designing & implementing a distributed event recognition and signalling system.
- Designing & implementing a distributed metrics subsystem and feedback control algorithms for distributed control.
- Build systems with arbitrary scale in mind e.g. millions of nodes.
You'll use standard software development best practices such as version control and participate in software development processes such as code and design reviews.
We pay competitively. While this position can be remote, you may be asked from time to time to travel to and work from the main office located in Redwood City, CA.
https://en.m.wikipedia.org/wiki/SM_EVM