As a long time Altera user, one of the biggest things that made me want to jump the fence to Xilinx was the MUCH stronger community and hobbyist uptake. Xilinx benefitted from a ton of people out there educating others on their behalf.
Trying to shrink that community seems like a pretty obvious error. The closest thing the Altera world ever had were the old Altera user forums, which were a gold-mine. Intel shut them down immediately on acquisition. I guess it's AMD's turn.
The HBM stacks are on-package for these parts, so you don't have to use any external I/O to interface with them.
You end up with a similar challenge accessing that much bandwidth internally from your FPGA logic though, it looks like the Xilinx HBM IP presents a set of 16 or 32 separate AXI interfaces, each of which gives you about 14.4GB/s of bandwidth (https://docs.amd.com/r/en-US/pg276-axi-hbm/Introduction).
PTP is a great choice when you need your time-sync to leave the software domain, for instance, locking an external PLL for frequency and phase aligned clocks.
PTP enabled MAC's and PHY's usually have a dedicated hardware output for a PPS (pulse-per-second) or faster clock, generated directly from the hardware PTP counters.
In the video world, we get great results synchronizing software events with NTP, but whenever you jump to a physical interface (DisplayPort, HDMI, SDI, etc.), NTP-based clocks are far too jittery.
I've seen some work using the PTP hardware in the MAC with the NTP protocol, a sort of hybrid approach, but don't have any first hand experience.
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Trying to shrink that community seems like a pretty obvious error. The closest thing the Altera world ever had were the old Altera user forums, which were a gold-mine. Intel shut them down immediately on acquisition. I guess it's AMD's turn.