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tamlin

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tamlin
·tahun lalu·discuss
Yes, I used VSS as a solo developer in the 90s. It was a revelation at the time. I met other VCS systems at grad school (RCS, CVS).

I started a job at MSFT in 2004 and I recall someone explaining that VSS was unsafe and prone to corruption. No idea if that was true, or just lore, but it wasn't an option for work anyway.
tamlin
·tahun lalu·discuss
Source Depot was based on Perforce. Microsoft bought a license for the Perforce source code and made changes to work at Microsoft scale (Windows, Office).

TFS was developed in the Studio team. It was designed to work on Microsoft scale and some teams moved over to it (SQL server). It was also available as a fairly decent product (leagues better than SourceSafe).
tamlin
·tahun lalu·discuss
Samsung and SK-Hynix have had specs and papers for a few years already for HBM and GDDR. e.g.

* https://www.servethehome.com/sk-hynix-ai-memory-at-hot-chips... * https://www.servethehome.com/samsung-processing-in-memory-te...

Not sure anyone has started using it in production.
tamlin
·tahun lalu·discuss
Yes, agree. Probably the main thing is the NPU is just a dedicated unit without the generality / complexity of a CPU and so able to crunch matmuls more efficiently.
tamlin
·tahun lalu·discuss
No worries, and no humble pie required. Peace, good happiness.
tamlin
·tahun lalu·discuss
Agree on NPU vs CPU memory bandwidth, but not sure about characterizing the GPU that way. GDDR is usually faster than DDR of the same generation, and on higher end graphics cards has a width bus width. A few GPUs have HBM and pretty much all datacenter ML accelerators (NVidia B200 / H100 / A100, Google TPU, etc). The PCIe bus between the host memory and GPU memory is a bottleneck for intensive workloads.

To perform a multiplication on CPU, even SIMD, that values have to fetched and converted to a form the CPU has multipliers for. This means smaller numeric types penalised. For a 128-bit memory bus, an NPU can fetch 32 4-bit values per transfer; the best case for a CPU is 16 8-bit values.

Details are scant on Microsoft's NPU, but it probably has many parallel multipliers; either in the form of tensor cores or a systolic array. The effective number of matmul's per second (or per memory operation) is higher.
tamlin
·tahun lalu·discuss
Rotor had it's own license:

https://en.wikipedia.org/wiki/Shared_Source_Common_Language_...

I have various snapshots of the Rotor 1 and 2 sources around and they have the SSCLI license. There is a file that contains BSD licensed code (pal\rotor_pal.h).
tamlin
·tahun lalu·discuss
Microsoft had a research version of the CLR called Rotor (2002) that predated Mono (2004). Rotor built for Windows, FreeBSD, and macOs, albeit with a not-very-open license.

When Mono came along, the internal position at Microsoft was surprisingly positive. There was a dev slide deck that went into Mono in some depth. And a telling slide that said it wasn't a threat because the performance wasn't competitive at the time.

https://en.m.wikipedia.org/wiki/Shared_Source_Common_Languag...

https://en.m.wikipedia.org/wiki/Mono_(software)
tamlin
·tahun lalu·discuss
A decent chunk of AI computation is the ability to do matrix multiplication fast. Part of that is reducing the amount of data transferred to and from the matrix multiplication hardware on the NPU and GPU; memory bandwidth is a significant bottleneck. The article is highlighting 4-bit format use.

GPUs are an evolving target. New GPUs have tensor cores and support all kinds of interesting numeric formats, older GPUs don't support any of the formats that AI workloads are using today (e.g. BF16, int4, all the various smaller FP types).

NPU will be more efficient because it is much less general an GPU and doesn't have any gates for graphics. However, it is also fairly restricted. Cloud hardware is orders of magnitude faster (due to much higher compute resources I/O bandwidth), e.g. https://cloud.google.com/tpu/docs/v6e.