Show HN: R8 Processor(hasaranga.com)
hasaranga.com
Show HN: R8 Processor
http://www.hasaranga.com/R8/
37 comments
Are there any FPGAs that can fit into the PCI slot of Thinkpads (specifically my X220). I want to play around with them but I don't want to lug around 30 development boards and cables.
Get an icestick (fpga on a USB stick). You can use an entire open source tool chain (thanks to great reverse engineering work) although I would use the default tools even if it implies running Windows in a VM.
Some other boards a pretty small. I have a Xilinx Spartan; really easy to carry around.
Some other boards a pretty small. I have a Xilinx Spartan; really easy to carry around.
Second the default tools. The open source tools are really cool, but especially if you're just starting out, the proprietary tools are much gentler in helping you debug your own mistakes.
I wouldn't say lattice tools are super helpful, I've spent more hours cursing icecube2 than I care to recall.
There is a design for one that will replace the cellular card. You need a BIOS firmware that will not whitelist PCI-E devices.
https://github.com/polysome/aggregate-1/blob/master/README.m...
https://github.com/polysome/aggregate-1/blob/master/README.m...
That looks exactly like what I'm looking for. Running Coreboot would probably work with something like this so that's what I'd do if someone ever actually sold these. I assume I don't need to take it out of my laptop to use it. Hopefully I can program/flash the SD card from the system.
Not that I know of. However, there's Avnet's Spartan-6 LX9 MicroBoard evaluation kit, which has a USB-stick form factor, is inexpensive, and is compatible with the free version of Xilinx's tools.
This [0] looks good but I wouldn't call it portable. If there was a case and it had some kind of conformal coating so it doesn't expload from slight moisture then I would say it would be a very good choice.
[0] - http://dangerousprototypes.com/blog/2011/04/22/avnet-spartan...
[0] - http://dangerousprototypes.com/blog/2011/04/22/avnet-spartan...
It's my understanding that you could use emulation as well in some development environments. That would forgo all hardware/cables/kits, etc.
how does verilog then translate onto a chip, does it try to fit it into the space?
are there any tutorials for this?
are there any tutorials for this?
be careful with trademark from ARM, they already have R5 and R7 cpus, I'm not sure about R8
The C.H.I.P. guys (and maybe Allwinner themselves) use R8 as a CPU name:
https://getchip.com/ http://linux-sunxi.org/Allwinner_SoC_Family#.22R.22-Series
https://getchip.com/ http://linux-sunxi.org/Allwinner_SoC_Family#.22R.22-Series
They do have an R8 core, but they don't have a trademark on that part of the name[1], they just have one for Cortex. However, the name should probably be changed for removing confusion anyways, because Renesas has an R8C series of CISC microcontrollers [2]. The namespace around single letter and then a number processor model is real crowded.
[1] https://www.arm.com/about/trademarks/arm-trademark-list/
[2] https://www.renesas.com/en-us/products/microcontrollers-micr...
[1] https://www.arm.com/about/trademarks/arm-trademark-list/
[2] https://www.renesas.com/en-us/products/microcontrollers-micr...
There is the Audi R8 sports car, but I guess this is unrelated enough?
Can use same name for a different product catigory. Same catogory -> somebody gonna geta hurt
Intel discovered to their cost that you can't trademark a number (hence 80486->pentium). Don't know if one letter is enough :-)
Unless it is relaterade to apple(s).
Nobody can trademark the name "Windows" as applied to actual windows. And I'm free to create a trademarked chain of "Windows" restaurants. But I can't call my operating system "Windows" and I'm on thin ice calling any other sort of computer program "Windows."
Clearly the day Audi is threatened by a processor they need to quit building cars.
Allwinner has an R8 IoT SoC based on the A13.
Cool project! I see lots of toy RISC CPUs but rarely anything CISCy. This sort of thing is great as a house-keeping core for bigger RTL designs, especially as it is synthesis-able.
Are you planning to extend the ISA at all?
Are you planning to extend the ISA at all?
I'm not sure if < 40 instructions should count as 'CISC' by any definition. Besides the instructions that are implemented fall squarely in the 'RISC' domain: low count, very few addressing modes, memory access separate from operations.
I sort of consider x86 ISAs barely CISCy - almost all x86 instructions that access memory involve a single address (so one TLB dip even if you're doing RMW) - this makes it easy to decompose instructions into uOPs.
IMHO 'Real' CISCs potentially have multiple memory addresses "add m1, m2, m3" sort of things and addressing modes that do double indirections (remember a worst case VAX instruction could generate [I think] 27 different TLB misses which meant that the smallest process had to have an at least 27 page minimum working set to let every program progress - for a RISC machine it's just 2)
Really though what happened between RISC/CISC was largely driven by a change in the relative speeds of memory and CPUs - CISCs made sense when memory bandwidth was low and heavy encoding reduced instruction bandwidth, RISCs (or RISCish including x86s) have come to dominate as caches moved on-chip and bandwidth soared
IMHO 'Real' CISCs potentially have multiple memory addresses "add m1, m2, m3" sort of things and addressing modes that do double indirections (remember a worst case VAX instruction could generate [I think] 27 different TLB misses which meant that the smallest process had to have an at least 27 page minimum working set to let every program progress - for a RISC machine it's just 2)
Really though what happened between RISC/CISC was largely driven by a change in the relative speeds of memory and CPUs - CISCs made sense when memory bandwidth was low and heavy encoding reduced instruction bandwidth, RISCs (or RISCish including x86s) have come to dominate as caches moved on-chip and bandwidth soared
"Move immediate value to memory address" seems like a prototypically CISCy operation to me.
Typical CISC is an instructions which uses both a load/store pipeline slot and an ALU pipeline slot. 'move immediate to address' just uses a load/store slot and fits into a normal risc microarchitecture; the reason you don't normally get it is encoding constraints: the address typically uses the instruction bits where the immediate would go.
Looking at the source, though, this processor uses a variable length instruction; so it is at least a bit CISCy.
Looking at the source, though, this processor uses a variable length instruction; so it is at least a bit CISCy.
Adding new instruction to this processor is pretty easy! But I'm little bit busy right now. I'll do it whenever I get free time!
What's the license?
it's free for personal and commercial use.
Perhaps you could add a mention of the license on the project page and/or at the top of the file?
If I'm understanding you right don't have a former license yet. You could use something like MIT, Apache 2.0, CC0, GPL, LGPL or WTFPL, that would fit your comment.
I think MIT or Apache 2.0 would be the safest choices (if you don't have a preference for GNU/copyleft licenses).
I'm afraid a HN comment won't hold up in court as proof I have a license to use a work.
If I'm understanding you right don't have a former license yet. You could use something like MIT, Apache 2.0, CC0, GPL, LGPL or WTFPL, that would fit your comment.
I think MIT or Apache 2.0 would be the safest choices (if you don't have a preference for GNU/copyleft licenses).
I'm afraid a HN comment won't hold up in court as proof I have a license to use a work.