Chip Ignite: Rapid IC Creation(efabless.com)
efabless.com
Chip Ignite: Rapid IC Creation
https://efabless.com/chipignite/2106q
9 comments
If you don't mind publishing your project as open source then there is the option to let Google pay for it:
https://efabless.com/open_shuttle_program/2
There are 40 slots, so you might not get selected. But the open shuttle uses the same software and framework as chip ignite.
https://efabless.com/open_shuttle_program/2
There are 40 slots, so you might not get selected. But the open shuttle uses the same software and framework as chip ignite.
I've had a chip design bouncing around in my head since the 1980s, now I can finally get it made. Thanks so much for posting this.
The idea is simple... a grid of 4x4 LUTs, each geographic neighbor has 1 bit in, and 1 bit out, there are 16 states, each with 4 outputs.
Turns out that this route-less FPGA can do some fairly amazing things, at least in theory. Now I intend to find out.
The really old blog I had about it - https://bitgrid.blogspot.com/
The idea is simple... a grid of 4x4 LUTs, each geographic neighbor has 1 bit in, and 1 bit out, there are 16 states, each with 4 outputs.
Turns out that this route-less FPGA can do some fairly amazing things, at least in theory. Now I intend to find out.
The really old blog I had about it - https://bitgrid.blogspot.com/
There have been FPGAs in the past which used the logic blocks for routing, including the Xilinx 6200. I think that was also the case for the Atmel AT40K FPGAs, but could be remembering wrong.
In fact, our project for the previous Google shuttle was an FPGA-like device which also routes data using logic cells. Here is an introduction to the idea:
https://github.com/fiberhood/MorphleLogic/blob/main/README_M...
It worked in simulation and the chip is currently scheduled to be shipped to us on September 6. There were 2 or 3 projects that were more conventional FPGAs.
In fact, our project for the previous Google shuttle was an FPGA-like device which also routes data using logic cells. Here is an introduction to the idea:
https://github.com/fiberhood/MorphleLogic/blob/main/README_M...
It worked in simulation and the chip is currently scheduled to be shipped to us on September 6. There were 2 or 3 projects that were more conventional FPGAs.
The Morphie blob looks like a special case of a 4x4LUT. I'd be interested to know how the chips work out.
There are some common features, but also differences that makes them a bit hard to compare directly.
An academic project that takes yet another approach to this design space is:
http://cba.mit.edu/projects/rala/
An academic project that takes yet another approach to this design space is:
http://cba.mit.edu/projects/rala/
Unfortunately, none of the links there go to anything, unless you have a username/password to sign in.
Here is a link to an "open access" copy of the 2010 RALA paper:
https://dspace.mit.edu/handle/1721.1/72349
https://dspace.mit.edu/handle/1721.1/72349
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They might not allow it (no chance of marketplace sales or follow-on volume), but if I were better off I'd drop the $10k or so and do something random just for the experience. Maybe a bunch of different little designs on one IC.