Ask HN: Is RISC-V getting any real traction, and if so where?
9 comments
I think they’re referring to the odd custom-ish embedded parts, e.g. Western Digital usage in mass produced storage devices that can afford novelty.
The problem is that there are really no current commodity embedded RISC-V architecture parts - Chinese dime-a-dozen pseudo-Cortex ripoffs don’t count - remotely comparable in performance/power to better current alternatives.
Benchmarks of SiFive’s high end are laughable, being grossly sub-RaspberryPi which is hardly ARM top of the line (and doesn’t claim to be such). As SiFive’s P550 hasn’t materialized beyond PR, one can hardly consider it real.
Unless some stealth startup appears with a real Zen/NeoVerse analog, I expect this triumph of hype over reality to continue.
The problem is that there are really no current commodity embedded RISC-V architecture parts - Chinese dime-a-dozen pseudo-Cortex ripoffs don’t count - remotely comparable in performance/power to better current alternatives.
Benchmarks of SiFive’s high end are laughable, being grossly sub-RaspberryPi which is hardly ARM top of the line (and doesn’t claim to be such). As SiFive’s P550 hasn’t materialized beyond PR, one can hardly consider it real.
Unless some stealth startup appears with a real Zen/NeoVerse analog, I expect this triumph of hype over reality to continue.
How would the P550 have "materialised"? It was only announced in June. It takes at least 12-18 months to go from a core being announced to someone incorporating it into an SoC and then manufacture that SoC, let alone have it in products in shops.
As is usual in the industry, any serious potential customer will have been able to get the full RTL for the core back in June or July, and evaluate its performance in simulators such as Verilator, or on FPGAs.
Claiming it's somehow not "real" is just stupid. There is no serious possibility that a core that boots Linux and runs SPEC etc in an FPGA won't work the same in a properly designed and manufactured SoC.
Benchmarks of the HiFive Unmatched are exactly what they should be given its A55-like microarchitecture -- a bit better than a Pi 3 and sometimes close to a Pi 4 on normal compiled C code. It doesn't have SIMD or specialised AES and SHA instructions, so of course benchmarks of that kind of thing are worse than a Pi. If that's important to you then of course don't buy one.
RISC-V International last month ratified a number of important extensions including Vector and crypto and those will start appearing in future chips.
There are several documented startups working on "M1 class" RISC-V cores, staffed with highly experience highly credible people such as Jim Keller or people who founded PA Semi and then developed ARM cores at Apple (including the M1).
There's no magic involved in making a top end RISC-V core, just money and good engineering.
As is usual in the industry, any serious potential customer will have been able to get the full RTL for the core back in June or July, and evaluate its performance in simulators such as Verilator, or on FPGAs.
Claiming it's somehow not "real" is just stupid. There is no serious possibility that a core that boots Linux and runs SPEC etc in an FPGA won't work the same in a properly designed and manufactured SoC.
Benchmarks of the HiFive Unmatched are exactly what they should be given its A55-like microarchitecture -- a bit better than a Pi 3 and sometimes close to a Pi 4 on normal compiled C code. It doesn't have SIMD or specialised AES and SHA instructions, so of course benchmarks of that kind of thing are worse than a Pi. If that's important to you then of course don't buy one.
RISC-V International last month ratified a number of important extensions including Vector and crypto and those will start appearing in future chips.
There are several documented startups working on "M1 class" RISC-V cores, staffed with highly experience highly credible people such as Jim Keller or people who founded PA Semi and then developed ARM cores at Apple (including the M1).
There's no magic involved in making a top end RISC-V core, just money and good engineering.
Embedded.
I am not sure it's inevitable at all. That said, it sure looks like ARM did, minus the license fees. RISC-V can enter niche markets where price / performance is necessary on the low end of price and or power.
Things are still early though. Extensions are one ambiguity. How many will crop up and what will using them look like? Does one take over the ISA essentially?
Math performance, due to no flags and multiple instructions needed where single ones or even just a few less will matter too. Not saying the devices won't perform. They will, just at the cost of code size impacting effective cache size.
And no device is really performing today.
I am not sure it's inevitable at all. That said, it sure looks like ARM did, minus the license fees. RISC-V can enter niche markets where price / performance is necessary on the low end of price and or power.
Things are still early though. Extensions are one ambiguity. How many will crop up and what will using them look like? Does one take over the ISA essentially?
Math performance, due to no flags and multiple instructions needed where single ones or even just a few less will matter too. Not saying the devices won't perform. They will, just at the cost of code size impacting effective cache size.
And no device is really performing today.
In 64 bit (which is what is important today for mobile and PCs etc), RISC-V has clearly the smallest code size of any ISA, by a considerable margin, with all the benefits of better cache usage you correct note that brings.
You don't have to take my word for it -- download the disk images for Fedora or Ubuntu for arm64, amd64, and riscv64 and run the "size" command on your selection of binaries.
riscv64 is consistently the smallest, and arm64 the largest.
You don't have to take my word for it -- download the disk images for Fedora or Ubuntu for arm64, amd64, and riscv64 and run the "size" command on your selection of binaries.
riscv64 is consistently the smallest, and arm64 the largest.
I wrote math performance specifically, because that code size is larger and didn't have to be, arguably shouldn't be.
The problem is that, when people say "math", they usually refer to HPC, or sometimes machine learning, or in very rare occasions, symbollic math. They usually don't mean arbitrary-precision math. In fact, I'm not aware of a single serious computation field that must depend on arbitray-precision math. Usually in HPC or ML, if your model overflows, then your model just overflowed.
So for those scenarios, I haven't heard of code-size problem argument against RISC-V.
So for those scenarios, I haven't heard of code-size problem argument against RISC-V.
It may be a performance problem more specifically. More instructions / result = more instruction fetches and cache space used = lower peak performance than there would be otherwise.
Who knows? Maybe an extension addresses this and becomes dominant.
It's just more wordy per result than it could be, and it seems a poor choice given all the other pretty great ones made.
Who knows? Maybe an extension addresses this and becomes dominant.
It's just more wordy per result than it could be, and it seems a poor choice given all the other pretty great ones made.
It is physically and logically impossible for any one practical ISA to optimally cover every one of the thousands of highly specialised application areas.
You, apparently, really really care about arbitrary-precision adds.
RISC-V is a general purpose ISA. It can do any computing task, just perhaps not optimally.
How non-optimal is it for arbitrary-precision adds? Or, more importantly, for the overall application that is a part of. No one who has raised this as a concern has shown any actual numbers. In fact they don't even show the actual loop doing the arbitrary-precision add, with loop control instructions, loads and stores. All they show is that a single "add-with-carry" instruction in some other ISAs translates to several instructions in RISC-V.
The problem, if any, in your application area can be solved by adding a single custom instruction to the ISA.
That doesn't sound like something fundamentally wrong with the ISA. Especially when that ISA is designed from the start to be extensible by users via adding custom instructions.
You, apparently, really really care about arbitrary-precision adds.
RISC-V is a general purpose ISA. It can do any computing task, just perhaps not optimally.
How non-optimal is it for arbitrary-precision adds? Or, more importantly, for the overall application that is a part of. No one who has raised this as a concern has shown any actual numbers. In fact they don't even show the actual loop doing the arbitrary-precision add, with loop control instructions, loads and stores. All they show is that a single "add-with-carry" instruction in some other ISAs translates to several instructions in RISC-V.
The problem, if any, in your application area can be solved by adding a single custom instruction to the ISA.
That doesn't sound like something fundamentally wrong with the ISA. Especially when that ISA is designed from the start to be extensible by users via adding custom instructions.
We will see. I think flags in general have enough advantages that the chip really should have them.
And it's not just an arbitrary Precision. There's a variety of constructs that will be longer.
And hey, it's not like I'm anti. We'll see where it all goes, and if it really does shake out like the proponents say, this will just be an academic matter.
I would rather some really good instructions be part of the base set just so they have broad coverage. The whole just add a rando instruction idea doesn't appeal to me at all.
And it's not just an arbitrary Precision. There's a variety of constructs that will be longer.
And hey, it's not like I'm anti. We'll see where it all goes, and if it really does shake out like the proponents say, this will just be an academic matter.
I would rather some really good instructions be part of the base set just so they have broad coverage. The whole just add a rando instruction idea doesn't appeal to me at all.
Thoughts?
[1] https://www.sifive.com/blog/risc-v-is-inevitable