Unpacking Xilinx 7-Series Bitstreams (2018)(kc8apf.net)

Unpacking Xilinx 7-Series Bitstreams (2018)

https://www.kc8apf.net/2018/05/unpacking-xilinx-7-series-bitstreams-part-1/

10 comments

Project X-Ray [1] and Project U-Ray [2] are the best source for configuration details that Xilinx/AMD doesn't publish. These projects focus, respectively, on the 7-series and UltraScale FPGAs.

[1]: https://f4pga.readthedocs.io/projects/prjxray/en/latest/

[2]: https://prjuray.readthedocs.io/en/latest/

uticus3 anni fa

Parts 2 and 3 are where it gets really interesting. Unfortunately no part 4 as promised in the Aug 2018 post.

[0] https://www.kc8apf.net/2018/05/unpacking-xilinx-7-series-bit...

[1] https://www.kc8apf.net/2018/08/unpacking-xilinx-7-series-bit...

userbinator3 anni fa

The big FPGA companies tend to be a bit lawyer-happy when you start publicly analysing their bitstream formats. I wonder if that's what happened.

imtringued3 anni fa

My hunch would be that knowing the bitstream format allows a competitor to reverse engineer your FPGA somehow. Otherwise I can't imagine what purpose it serves. The most likely reason is that there are some IP cores with complicated licensing schemes and the encryption acts as some form of DRM.

Brian_K_White3 anni fa

aliens: "One of them figures out something. They don't tell anyone else how it works. Countless others waste countless time and effort trying to figure out the same thing that has already been figured out. The others punish the first for this by giving them all their fishes."

imstate3 anni fa

This interesting.

A while back I wrote a C++ library to load a bitsteam virtex ultrascale through jtag using FTDIs d2xx driver.

Intel is more closed in the JTAG opcodes for programming the device. I was able to read IDCODES out of the JTAG.

latchkey3 anni fa

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irdc3 anni fa

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ktta3 anni fa

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