OpenPOWER Foundation – Open-Source / Open Hardware PowerPC CPU ISA(openpowerfoundation.org)
openpowerfoundation.org
OpenPOWER Foundation – Open-Source / Open Hardware PowerPC CPU ISA
https://openpowerfoundation.org/
47 comments
No - essentially a modern CPU is composed of multiple blocks, not just the actual CPU core. Some of those IP blocks will be closed source, often from third party vendors, and sometimes that means proprietary software blobs to interact with them (whether because the documentation to configure them is proprietary, or because you need to load proprietary microcode or firmware).
The OpenPOWER foundation does not deal with entire CPU module / SoC component, and as such it's not really in their bailwick.
The issue with POWER 10 cpus was that at least two important blocks without which the CPUs are essentially useless involved such third party components that required closed source firmware blobs to initialize.
One of them was effectively the only OMI<->DDR4 (iirc) memory interface (OMI - serial link for memory, successor of POWER8/9 Centaur link), and the other was I think Synopsys' PCI-Express Root Ports
The OpenPOWER foundation does not deal with entire CPU module / SoC component, and as such it's not really in their bailwick.
The issue with POWER 10 cpus was that at least two important blocks without which the CPUs are essentially useless involved such third party components that required closed source firmware blobs to initialize.
One of them was effectively the only OMI<->DDR4 (iirc) memory interface (OMI - serial link for memory, successor of POWER8/9 Centaur link), and the other was I think Synopsys' PCI-Express Root Ports
link ?
So what exactly does OpenPOWER grant me? If I create a CPU core design that implements the same ISA as, say, the PowerPC G5 chip used in Macs from 2002-2012, can I sell it? Or can I open-source it? Or is OpenPOWER incompatible with the PowerPC line?
PowerPC and POWER are not the same. PowerPC was created because Apple allied with IBM, but they wanted Motorola as a supplier. So they basically changed Motorola own RISC chip into something POWER like.
OpenPOWER used to be restricted, but because RISC-V absolutely crush the OpenPOWER fake marketing with being really open, OpenPOWER (like MIPS) after a few years have changed and are now more like RISC-V.
OpenPOWER used to be restricted, but because RISC-V absolutely crush the OpenPOWER fake marketing with being really open, OpenPOWER (like MIPS) after a few years have changed and are now more like RISC-V.
No, The AIM alliance's goal was to create a standard Power architecture: https://en.wikipedia.org/wiki/AIM_alliance
PPC Mac is the same PPC that Motorola developed and marketed. The key difference lies in the platform as Power PC is just a CPU ISA, it does not define a platform which includes hardware layout and booting. So you cant just buy a Motorola chip and boot MacOS because MacOS expects a Power Macintosh complete with Power Macintosh hardware and firmware.
Arm and Risc-V also do not define a platform. IBM is the one who developed a standard hardware and firmware design, the BIOS, for the Intel 8086 and thus the PC was born. The PC platform is why we think of computers as general purpose machine that boot any OS. Outside of that ecosystem it's a big mess. Arm and Risc-v do not define platforms which is not a good situation.
PPC Mac is the same PPC that Motorola developed and marketed. The key difference lies in the platform as Power PC is just a CPU ISA, it does not define a platform which includes hardware layout and booting. So you cant just buy a Motorola chip and boot MacOS because MacOS expects a Power Macintosh complete with Power Macintosh hardware and firmware.
Arm and Risc-V also do not define a platform. IBM is the one who developed a standard hardware and firmware design, the BIOS, for the Intel 8086 and thus the PC was born. The PC platform is why we think of computers as general purpose machine that boot any OS. Outside of that ecosystem it's a big mess. Arm and Risc-v do not define platforms which is not a good situation.
>RISC-V do not define a platform.
With a very strictly narrow lens, RISC-V is just the ISA.
In reality, a major part of RISC-V International standardization effort goes into non-ISA specs, which include the platform specs, a major focus from early on.
This is e.g. how I am able to run my VisionFive2 with a generic Debian kernel. It would be unthinkable on ARM.
With a very strictly narrow lens, RISC-V is just the ISA.
In reality, a major part of RISC-V International standardization effort goes into non-ISA specs, which include the platform specs, a major focus from early on.
This is e.g. how I am able to run my VisionFive2 with a generic Debian kernel. It would be unthinkable on ARM.
It's unfortunate that the spec avoided designing a clean solution to a simple problem and drags in the complexity of PC baggage such as ACPI and UEFI to avoid doing work.
>to avoid doing work
The problem with "doing work" is that work does take time.
Being late means widespread non-standardized, bespoke vendor specific solutions. Exactly the one thing RISC-V International strongly wants to avoid.
Won't go into judging ACPI and UEFI, and how misunderstood or desirable they are.
RISC-V chose to adopt these, and to standardize what the baseline platform is, and specify how ACPI and UEFI are implemented.
The problem with "doing work" is that work does take time.
Being late means widespread non-standardized, bespoke vendor specific solutions. Exactly the one thing RISC-V International strongly wants to avoid.
Won't go into judging ACPI and UEFI, and how misunderstood or desirable they are.
RISC-V chose to adopt these, and to standardize what the baseline platform is, and specify how ACPI and UEFI are implemented.
Even if some their ideas are desirable, the execution very much isn't.
Arm does indeed define a platform, it's called SBSA
https://en.wikipedia.org/wiki/Server_Base_System_Architectur...
https://en.wikipedia.org/wiki/Server_Base_System_Architectur...
You are right but the only systems I have seen that support it are servers or expensive workstations from Ampere and maybe 1 or 2 others. I feel like 99% of the ARM based computing devices that people can buy for under $2000 have non standard boot systems. Do any of the Qualcomm ARM based laptops support an open boto standard?
In contrast I feel like 99% of x86 based computing devices under $2000 have standard boot systems where anyone can boot windows or Linux on them with minimal issues.
In contrast I feel like 99% of x86 based computing devices under $2000 have standard boot systems where anyone can boot windows or Linux on them with minimal issues.
Please point me to a cost effective general purpose Arm computer that uses SBSA.
I know this board and it is not general purpose. This is not designed to watch videos, play games or browse the web. Again, show me a general purpose Arm computer that is made for the average user.
It looks like something for a router or network switch. No graphics but it does have an open PCIE x8 slot. The ARM A72 is now a 9 year old CPU core. The reviews of this board are all from 4 years ago. It looks like their newer similar products have a Ryzen core that is a lot faster.
Here is an Ampere workstation but it is $3300. In my other post in this thread I mentioned $2000 as the price limit. Most consumers are not going to spend more than that on a computer.
https://system76.com/desktops/thelio-astra-a1.1-n1/configure
Here is an Ampere workstation but it is $3300. In my other post in this thread I mentioned $2000 as the price limit. Most consumers are not going to spend more than that on a computer.
https://system76.com/desktops/thelio-astra-a1.1-n1/configure
> PowerPC and POWER are not the same.
AIUI PowerPC is essentially an extended (original) POWER.
The AIM alliance defined PowerPC which had 32bit and 64 bit modes, and IBM also added ISA extensions - the PowerPC AS or "Amazon" - for its AS/400 line.
When the POWER3 came around, the original 32Bit POWER ISA was deprecated, but still included for backwards compatibility. So all POWER chips since then implement the PowerPC ISA.
AIUI PowerPC is essentially an extended (original) POWER.
The AIM alliance defined PowerPC which had 32bit and 64 bit modes, and IBM also added ISA extensions - the PowerPC AS or "Amazon" - for its AS/400 line.
When the POWER3 came around, the original 32Bit POWER ISA was deprecated, but still included for backwards compatibility. So all POWER chips since then implement the PowerPC ISA.
Thanks for clearing that up.
What exactly is the selling point of the Power ISA? Why would I want to use it over RISC-V?
It is aimed at a completely different market from RISC-V.
RISC-V advantages is that it is an incredible simple and extensible architecture aimed at low power / embedded use cases. It is also easy to customize (similar to ARM) for specific use cases.
Power ISA is a super computer chip, while RISC-like, has a lot of legacy baggage and isn't designed for low-power nor is it designed for embedded situations. It also is not designed for customizability, it is more like a monolith project.
Power ISA will have space at the top of the market for very high performance CPUs. But I think it will be stuck there as there are no benefits over RISC-V in the areas where RISC-V is growing right now.
RISC-V advantages is that it is an incredible simple and extensible architecture aimed at low power / embedded use cases. It is also easy to customize (similar to ARM) for specific use cases.
Power ISA is a super computer chip, while RISC-like, has a lot of legacy baggage and isn't designed for low-power nor is it designed for embedded situations. It also is not designed for customizability, it is more like a monolith project.
Power ISA will have space at the top of the market for very high performance CPUs. But I think it will be stuck there as there are no benefits over RISC-V in the areas where RISC-V is growing right now.
That isn’t actually true. I‘ve personally worked on an embedded POWER processor https://github.com/electronicvisions/nux. It is used as a dual core embedded micro-controller in a neuromorphic chip. Each core has just 16kB of memory on chip and 4kB instruction cache. POWER has subsets of the instruction set which have a gcc and llvm target and are well suited for embedded use cases.
Main advantage of RISCV at this point is that it has a larger community. But at the time it didn’t even have a vector instruction set, whereas we could easily modify the POWER one for our purposes.
Main advantage of RISCV at this point is that it has a larger community. But at the time it didn’t even have a vector instruction set, whereas we could easily modify the POWER one for our purposes.
RISC-V is absolutely not and never has been 'aimed at low power / embedded'. Literally from the very beginning the target was 'be an ISA for everything'. Its just natural that simpler things were standardized first and came to market first.
That POWER is better at top of the market is highly questionable, every new startup coming into the high performance space has universally picked RISC-V over OpenPOWER.
Also, nowadays even complex ISA were fine for embedded. The cost difference for stuff like that is tiny. Its really just about how many options do you have in the market, both open and closed. And that's where RISC-V by now simply has more.
OpenPOWER was only fake open for a long time, while marketing itself as open. Only when they were totally getting crushed, did they update and are more like RISC-V, but it was many years to late.
That POWER is better at top of the market is highly questionable, every new startup coming into the high performance space has universally picked RISC-V over OpenPOWER.
Also, nowadays even complex ISA were fine for embedded. The cost difference for stuff like that is tiny. Its really just about how many options do you have in the market, both open and closed. And that's where RISC-V by now simply has more.
OpenPOWER was only fake open for a long time, while marketing itself as open. Only when they were totally getting crushed, did they update and are more like RISC-V, but it was many years to late.
> Its just natural that simpler things were standardized first and came to market first.
Which isn't that different than what I am saying.
RISC-V is marketing towards low-power/embedded right now because it doesn't have performant cores. https://benhouston3d.com/blog/risc-v-in-2024-is-slow
Power ISA was not focused on this market, its historical market was high performance computing.
Which isn't that different than what I am saying.
RISC-V is marketing towards low-power/embedded right now because it doesn't have performant cores. https://benhouston3d.com/blog/risc-v-in-2024-is-slow
Power ISA was not focused on this market, its historical market was high performance computing.
Freescale PowerQUICC fans say whaaaaaat?
Power ISA absolutely was used in embedded contexts for years. Decades even.
---------
Instruction sets aren't very important actually. Like yeah, compiler infrastructure helps but a lot of embedded decision making is about peripherals.
PowerQUICC had powerful and extendable I/O that could be customized to many different needs. And I believe the bulk of those benefits stay over to the updated ARM chip QorIQ (as NXP bought FreeScale and seems to have prioritized ARM).
Power ISA absolutely was used in embedded contexts for years. Decades even.
---------
Instruction sets aren't very important actually. Like yeah, compiler infrastructure helps but a lot of embedded decision making is about peripherals.
PowerQUICC had powerful and extendable I/O that could be customized to many different needs. And I believe the bulk of those benefits stay over to the updated ARM chip QorIQ (as NXP bought FreeScale and seems to have prioritized ARM).
After Motorola has abandoned totally (MC88k, M.core) or partially (MC68k => Coldfire) its older ISAs and it has transitioned to using the POWER/PowerPC ISA, it has applied it to the market in which they was interested, designing many kinds of microcontrollers with it, mainly for the automotive and communications markets, where microcontrollers with higher performance were required. Around the same time IBM has also introduced a series of microcontrollers based on the POWER ISA (PowerPC 4xx).
However, when the POWER ISA has initially been designed, before its launch in 1990, its target were high-end scientific workstations and servers made by IBM. The idea of using it in embedded computers has come much later, when the increased density achievable in integrated circuits has made that possible.
However, when the POWER ISA has initially been designed, before its launch in 1990, its target were high-end scientific workstations and servers made by IBM. The idea of using it in embedded computers has come much later, when the increased density achievable in integrated circuits has made that possible.
Sure. But the embedded PowerQUICC chips were in use between the years 199x and 201x, and are still manufactured today in 2025.
My overall point is that Power ISA has a long history as both high performance compute AND embedded (be it industrial, automotive, or space embedded).
Maybe in the late 1980s POWER was high performance only. But there's a big history here and it's weird to see this discussion ignore Power ISA's long embedded history.
-------
Does OpenPower have a chance today? I dunno. Obviously the hype is in RISC-V and maybe a bit of ARM. But it's not a bad ISA and Power used to target embedded not very long ago
My overall point is that Power ISA has a long history as both high performance compute AND embedded (be it industrial, automotive, or space embedded).
Maybe in the late 1980s POWER was high performance only. But there's a big history here and it's weird to see this discussion ignore Power ISA's long embedded history.
-------
Does OpenPower have a chance today? I dunno. Obviously the hype is in RISC-V and maybe a bit of ARM. But it's not a bad ISA and Power used to target embedded not very long ago
RISC-V has obviously been initially designed with the only purpose of being extremely simple to implement, simple enough to be implementable by students.
Nothing else can justify the weird choices made in designing RISC-V.
The idea to use RISC-V in actually useful devices must have come only after the initial design and for this purpose the only advantage of RISC-V versus designing some proprietary CPU core is that for RISC-V there already exists a significant amount of tools for software development, i.e. linkers, assemblers, compilers, debuggers, a few optimized libraries etc.
This advantage of RISC-V is extremely important, because developing compilers and all the other required software tools for any new ISA requires much more work and resources than the hardware design of a CPU core implementing it.
However, it is sad that the first ISA with a permissive license allowing it to be used by everyone everywhere has been one so bad as RISC-V.
It is absurd to claim that the target of RISC-V is to 'be an ISA for everything', when it does not even have adequate means for detecting integer overflow, a feature that existed even in much smaller ancient 8-bit microprocessors, like Motorola MC6800 (1974) and Zilog Z80 (1976).
Startups choose RISC-V because it is a fashionable buzzword good for pleasing possible investors and because their team does not include anyone with experience in low-level assembly programming or compiler back-end implementation, the only people who can assess the quality of an ISA.
Nothing else can justify the weird choices made in designing RISC-V.
The idea to use RISC-V in actually useful devices must have come only after the initial design and for this purpose the only advantage of RISC-V versus designing some proprietary CPU core is that for RISC-V there already exists a significant amount of tools for software development, i.e. linkers, assemblers, compilers, debuggers, a few optimized libraries etc.
This advantage of RISC-V is extremely important, because developing compilers and all the other required software tools for any new ISA requires much more work and resources than the hardware design of a CPU core implementing it.
However, it is sad that the first ISA with a permissive license allowing it to be used by everyone everywhere has been one so bad as RISC-V.
It is absurd to claim that the target of RISC-V is to 'be an ISA for everything', when it does not even have adequate means for detecting integer overflow, a feature that existed even in much smaller ancient 8-bit microprocessors, like Motorola MC6800 (1974) and Zilog Z80 (1976).
Startups choose RISC-V because it is a fashionable buzzword good for pleasing possible investors and because their team does not include anyone with experience in low-level assembly programming or compiler back-end implementation, the only people who can assess the quality of an ISA.
The reasoning for this choice in the base ISA is discussed in the RISCV ISA manual, Section 2.4 on "Integer Computational Instructions" [1]. Given that RISCV is a modular ISA, it should be possible in principle to have suitable ISA extensions that do integer overflow detection.
Maybe the absence of such an extension in 2025 indicates that this is not a pressing need for many RISC-V users?
[1] https://lists.riscv.org/g/tech-unprivileged/attachment/535/0...
[1] https://lists.riscv.org/g/tech-unprivileged/attachment/535/0...
While very convenient to quickly link some ancient draft spec, let's try and stick to the actual ratified specifications[0].
Of course, the rationale is still there in section 2.4 of the current (20250508) ratified version of The RISC-V Instruction Set Manual Volume I: Unprivileged ISA.
0. https://riscv.org/specifications/ratified/
Of course, the rationale is still there in section 2.4 of the current (20250508) ratified version of The RISC-V Instruction Set Manual Volume I: Unprivileged ISA.
0. https://riscv.org/specifications/ratified/
You should learn about the history of RISC-V. RISC-V was initially designed to do research on advanced instructions architectures, like Vectors. So writing 64 bit chips with large vector engines was literally the initial design goal. And they deliberately went threw all historical bad ideas that were known to cause issues in out-of-order designs because the knew they wanted to do research on that as well. So its quite simply a historically well documented fact.
But they needed a simple base ISA that they could extend in different ways because different people planned on doing different kind of research on top.
When they then realized their was a need for a permissive license ISA that would be used be people outside of Berkley, like that they formulated a clear goal that is in all their early presentations, and it was "be the ISA for everything".
> when it does not even have adequate means for detecting integer overflow
Seems adequate for 1000s of companies who use RISC-V.
There are pros and cons of not having it, and the argument that 'X other design had feature Y' isn't an actual argument. Nobody has ever denied that they could have added that, its simply because they didn't want to.
> because it is a fashionable buzzword
I'm sure you are so much smarter then Jim Keller and David Dizel ...
But they needed a simple base ISA that they could extend in different ways because different people planned on doing different kind of research on top.
When they then realized their was a need for a permissive license ISA that would be used be people outside of Berkley, like that they formulated a clear goal that is in all their early presentations, and it was "be the ISA for everything".
> when it does not even have adequate means for detecting integer overflow
Seems adequate for 1000s of companies who use RISC-V.
There are pros and cons of not having it, and the argument that 'X other design had feature Y' isn't an actual argument. Nobody has ever denied that they could have added that, its simply because they didn't want to.
> because it is a fashionable buzzword
I'm sure you are so much smarter then Jim Keller and David Dizel ...
>It is aimed at a completely different market from RISC-V.
Not possible. RISC-V is aimed at absolutely everything.
Thus leaving no sizable niche exclusive to POWER ISA.
Not possible. RISC-V is aimed at absolutely everything.
Thus leaving no sizable niche exclusive to POWER ISA.
I feel like regardless of what you can accomplish with it will be drowned by having to deal with IBM's brilliant handling of their products.
The only occasions I interacted with POWER was in projects where the client was happily deploying bog standard enterprise amd64 servers running Linux to replace it.
The only occasions I interacted with POWER was in projects where the client was happily deploying bog standard enterprise amd64 servers running Linux to replace it.
You can accomplish the same task in substantially fewer instructions, leading to higher performance for a given level of design effort.
Also a more developed software ecosystem.
Also a more developed software ecosystem.
>You can accomplish the same task in substantially fewer instructions, leading to higher performance for a given level of design effort.
The statement is true and favorable to RISC-V, as it is the one with lowest instruction count and code size; RISC-V wins, and it is not even close.
>Also a more developed software ecosystem.
Historically true, but right now the momentum is with RISC-V, and it is absolutely is catching up, and no longer a point of contention.
e.g. Debian is the largest Linux distribution by its library of packaged software. There, RISC-V has already overtaken[0] it in available package count.
0. https://buildd.debian.org/stats/graph-week-big.png
The statement is true and favorable to RISC-V, as it is the one with lowest instruction count and code size; RISC-V wins, and it is not even close.
>Also a more developed software ecosystem.
Historically true, but right now the momentum is with RISC-V, and it is absolutely is catching up, and no longer a point of contention.
e.g. Debian is the largest Linux distribution by its library of packaged software. There, RISC-V has already overtaken[0] it in available package count.
0. https://buildd.debian.org/stats/graph-week-big.png
The community behind POWER has long been overtaken by RISC-V.
This can easily be seen reflected in Debian (largest distribution by package collection), where RISC-V has recently overtaken[0] ppc64 as the third largest ISA in available software.
The expectation is that RISC-V will continue to climb and eventually overtake ARM and x86.
RISC-V is inevitable.
0. https://buildd.debian.org/stats/graph-week-big.png
This can easily be seen reflected in Debian (largest distribution by package collection), where RISC-V has recently overtaken[0] ppc64 as the third largest ISA in available software.
The expectation is that RISC-V will continue to climb and eventually overtake ARM and x86.
RISC-V is inevitable.
0. https://buildd.debian.org/stats/graph-week-big.png
Why the focus on Risc-V when the Power architecture already has high-performance cores? Genuine questions.
OpenPOWER was created to sell chips more then anything else. But many people don't just want some stanard 'high performance' chip. There are many different kinds of high-performance chip. A high-performance chip, for a car, a gaming computer, a AI chip or a cloud chip that runs VM are all different.
There is simply not that amount of options in the POWER market. Its a restrictive set of vendors.
Pretty much every new startup designing high performance chips picked RISC-V. And they optimize their chips for specific use-cases.
In addition, the software ecosystem for RISC-V is arguable already better then POWER. And many companies and universities are working together on making it first class. Android is going to RISC-V, it will never be on POWER.
So if you were to design something for consumers, not going with RISC-V would be crazy.
RISC-V is also evolving far more quickly. There are like 80 working groups working on improvements all in the open. The amount of companies working on POWER is tiny in comparison.
There is simply not that amount of options in the POWER market. Its a restrictive set of vendors.
Pretty much every new startup designing high performance chips picked RISC-V. And they optimize their chips for specific use-cases.
In addition, the software ecosystem for RISC-V is arguable already better then POWER. And many companies and universities are working together on making it first class. Android is going to RISC-V, it will never be on POWER.
So if you were to design something for consumers, not going with RISC-V would be crazy.
RISC-V is also evolving far more quickly. There are like 80 working groups working on improvements all in the open. The amount of companies working on POWER is tiny in comparison.
Power and RISC-V are going after different markets.
While Power is IRSC has a lot of legacy baggage that makes it significantly more complex that RISC-V (which is clean slate and purposely simplified.) It is also definitely not optimized for low power situations / embedded.
It is basically super computer chip.
Also unlike ARM and RISC-V it isn't designed to be extensible/customized by users. It is more monolithic.
While Power is IRSC has a lot of legacy baggage that makes it significantly more complex that RISC-V (which is clean slate and purposely simplified.) It is also definitely not optimized for low power situations / embedded.
It is basically super computer chip.
Also unlike ARM and RISC-V it isn't designed to be extensible/customized by users. It is more monolithic.
I wouldn't say "super computer" chip (or at least "supercomputer")...
I've read the definition of a supercomputer as "some computer that takes specific domain, compute-bound problems and turns them into IO bound problems." (Implicitly, in that statement is the second statement of "and they have a ton of IO too). They're not really general purpose computers, and likely you'd be able to use risc-v or anything else, with specialized hardware, as the basis of a "supercomputer".
The power platform, on the other-hand (I'll create a new word here) is a foundation for a "SuperEnterprise(tm)" computer.
Power has insane / awesome things like "oh, you can use the ECC bits for ECC and hardware memory tagging[1]." Eventually such things may trickle down to things like ARM or RISC-V, but they're pioneered at the top of the enterprise mountain and trickle down...
[1]https://www.devever.net/~hl/ppcas
I've read the definition of a supercomputer as "some computer that takes specific domain, compute-bound problems and turns them into IO bound problems." (Implicitly, in that statement is the second statement of "and they have a ton of IO too). They're not really general purpose computers, and likely you'd be able to use risc-v or anything else, with specialized hardware, as the basis of a "supercomputer".
The power platform, on the other-hand (I'll create a new word here) is a foundation for a "SuperEnterprise(tm)" computer.
Power has insane / awesome things like "oh, you can use the ECC bits for ECC and hardware memory tagging[1]." Eventually such things may trickle down to things like ARM or RISC-V, but they're pioneered at the top of the enterprise mountain and trickle down...
[1]https://www.devever.net/~hl/ppcas
I guess I was referring to the fact that Power ISA chips were dominant at once time (prior to the rise of x86 chips) in the TOP 500 listings:
https://en.wikipedia.org/wiki/TOP500#/media/File:Processor_f...
They have faded from that over time from this niche. I do not know where they excel now.
https://en.wikipedia.org/wiki/TOP500#/media/File:Processor_f...
They have faded from that over time from this niche. I do not know where they excel now.
If you're a student in a microarchitecture class who has to implement a core in a semester then the simplicity of RISC-V makes it a much better choice. And if you're a grad student trying to try out some idea in your thesis then you should also choose RISC-V for the same reason.
If you're creating a microcontroller for a specific product then RISC-V's ability to only implement the hardware features you need is a big benefit and its compressed instructions let you save money using fewer RAM chips.
If you're creating a microcontroller for a specific product then RISC-V's ability to only implement the hardware features you need is a big benefit and its compressed instructions let you save money using fewer RAM chips.
The people I know using RISC-V don't want a high performance core. They want a very small area low power core for things like PCIE and DDR link training.
[deleted]
>"By open sourcing and developing on the POWER ISA - one of the most sophisticated processor architectures available - the OpenPOWER Foundation is democratizing access and extending the reach of the RISC-based architecture.'
Open for All
With more than 350 members collaborating regularly, the entire semiconductor industry - from global organizations with deep expertise to individual creators with a new lens - can innovate with choice and build and develop across the full Hardware and Software stack."
Related:
https://en.wikipedia.org/wiki/Power_ISA
https://en.wikipedia.org/wiki/Power10
https://www.itjungle.com/2024/12/02/power11-takes-memory-ban...
Open for All
With more than 350 members collaborating regularly, the entire semiconductor industry - from global organizations with deep expertise to individual creators with a new lens - can innovate with choice and build and develop across the full Hardware and Software stack."
Related:
https://en.wikipedia.org/wiki/Power_ISA
https://en.wikipedia.org/wiki/Power10
https://www.itjungle.com/2024/12/02/power11-takes-memory-ban...
Would these pose a problem for the this foundation?