Quantum dot qubit using High NA EUV lithography(imec-int.com)
imec-int.com
Quantum dot qubit using High NA EUV lithography
https://www.imec-int.com/en/press/world-first-imec-presents-quantum-dot-qubit-device-using-high-na-euv-lithography
5 comments
> Many people I talk to (laypeople like me) seem to think that QC is imminent and we need to prepare for it now.
prepare in what ways? preparing for a CRQC to maybe appear sooner-rather-than later means moving to PQ encryption ~now; there are probably other less rational ways people 'prepare'
prepare in what ways? preparing for a CRQC to maybe appear sooner-rather-than later means moving to PQ encryption ~now; there are probably other less rational ways people 'prepare'
They did, just not disclosing how many and in what configuration:
> Imec has succeeded in fabricating a functioning network of qubits with gaps of barely 6 nanometers. Thanks to the nanoscale of this hardware component, millions of quantum bits can theoretically be integrated onto a single chip.
> This demonstration builds on imec’s previous results with silicon quantum dot spin qubits, which already demonstrated that CMOS-compatible processes can lead to low charge noise and stable qubit operation. By adding High NA EUV lithography to the production process, the focus shifts from individual demonstration devices in the lab to 300mm fab-compatible [0], reproducible quantum bits.
Based on their previous publication from 2025 that used 0.33 NA EUV, I'd expect another 3x5 qubit device operating in a 10 mK environment, or something similar.
[0] "300 mm fab" being one thing, which these are then compatible with, in case anyone else was as confused reading this as I was. 300 mm (~1 ft) is the size (diameter) of the wafer.
> Imec has succeeded in fabricating a functioning network of qubits with gaps of barely 6 nanometers. Thanks to the nanoscale of this hardware component, millions of quantum bits can theoretically be integrated onto a single chip.
> This demonstration builds on imec’s previous results with silicon quantum dot spin qubits, which already demonstrated that CMOS-compatible processes can lead to low charge noise and stable qubit operation. By adding High NA EUV lithography to the production process, the focus shifts from individual demonstration devices in the lab to 300mm fab-compatible [0], reproducible quantum bits.
Based on their previous publication from 2025 that used 0.33 NA EUV, I'd expect another 3x5 qubit device operating in a 10 mK environment, or something similar.
[0] "300 mm fab" being one thing, which these are then compatible with, in case anyone else was as confused reading this as I was. 300 mm (~1 ft) is the size (diameter) of the wafer.
If you want to test if scaling works, you gotta scale it first.
Lemme guess. No Shor?
I’m still sceptical if quantum will take off in the foreseeable future if ever. Many people I talk to (laypeople like me) seem to think that QC is imminent and we need to prepare for it now.
We are still in the beginning stages of understanding whether scalable architectures are physically manufacturable at all.