I agree with afarrell that lying is not advisable. Lying is a very bad thing. Convincing someone else to do a bad thing is even worse.
The method I used when I was Software Development Manager was to ask one of the programmers how long he thought it should take (or estimate it myself). Then I told management that it would take 3 times that long. We usually could make that deadline but it was often close and sometimes a little late. I have since learned that it will take PI times as long as you think.
Telling the programmers that they have half as long does no good. They will not write code any faster. It may even distress them and a distressed programmer produces less code causing it to take longer.
FYI
Consider carefully what I say; my first computer program compiled and ran in the summer of 1967. I have typed in a program while both Bill Gates and Paul Allen watched over my shoulder. I'm retired now but still work daily on a subgame for minetest.
I am more trusting of naturally occuring substances than I am of chemicals that do not occur in nature cooked up in labs of big pharmaceutical companies.
These are some interesting observations regarding music and machine learning. It has been my experience that the majority of the output of ML music generators falls into the category I would classify as noise.
I briefly experimented with procedural music generation many years ago and will relate my experience in the hope that some may find it interesting or take inspiration from it.
I had read the Byte magazine article called "A Travesty Generator for Micros." which works with text files and realized that Markov chains could be applied either to whole word or individual letters. Sufficiently long chains of letters almost always produce actual words. Sufficiently long chains of words generally produce complete (although nonsensical) sentences. Excessively long chains copy the input to the output. See [1] and [2]
At the time I was playing LOTRO [3][4] which uses ABC files [5] which are a text representation of music. I used the .abc files as input to the travesty program and got very interesting output. I used the rescan method which reads the input file for each note to output. It is slow but uses far less memory than the array method which reads the input once and generates a complete table of all transitions.
Running travesty on a single .abc file produces an output which is very similar to the input and only mildly interesting. Chaining together 2 or more input files is when it gets more interesting. It did not work well unless the input files had the same key signature.
I considered the possibility of transposing all input files to a common key signature but did not implement it. Nearly all music representation is an abstraction of the music. Music is generally quantized into notes of the even tempered 12 note scale. The tune is recognizable regardless of the instrument it is played on. I wondered whether there were further abstractions which could be used similar to the way that either letters or words could be used for text but am not sufficiently musical that I could discover them.
If you try this I think you will quickly get results which encourage you to continue.
You might want to try the free game Minetest [1]. It is very similar to Minecraft but the basic version, minetest_game, has no animals. You can add mods that give you animals if you want them but they are not necessary. There are hundreds of open source mods to choose from or you can write your own mods in Lua. I learned Lua by examining the mods that come with the game and changing them. You can play in a mode where you can't take any damage. Multiplayer games can enable or disable PvP.
I had considered this as a possibility following much the same train of thought expressed by abakker but because it diverges from most common practice (and from mathematics) and because I was unsure whether anyone would actually want it, I had not really considered using it.
While reading the article and the comments I realized that it will work perfectly in my NISC processor [1]. I just need to update my specification.
To extend the simple first specification to include multiply is very simple. I just need to have a MUL register which, when written, multiplies the written value by the value in the accumulator with the low part of the result being left in the ACC and the high part in the MUL register.
Extending to include integer divide is a little more complicated. I will have to add a DIV register and a DIVEX register. Writing to DIV will divide the value in the ACC by the value written leaving the result in the ACC and the remainder in the DIV register. DIVEX will contain the address of the routine to call when division by zero is attempted which means that DIVEX must be loaded before division is used. If I specify that DIVEX is initialized to zero by the hardware and that DIVEX==0 means that divide by zero leaves zero in the ACC and the remainder (former contents of ACC) is left in the DIV register then 1/0 = 0 will be the default behavior with the ability to change that behavior simply by writing the address of the divide exception handler to the DIVEX register.
I leave it as an exercise for the reader to determine how to deal with this in high level languages. I can fully support it in machine code and assembly language.
For the rest of the article start by reading https://en.wikipedia.org/wiki/Datapoint_2200
Datapoint allowed Intel to continue development with the same architecture but required all future processors to have a shuffled instruction set. The mov group on the 8008 and the 2200 was octal 3ds with d being the destination register and s being the source register. The first digit 3 got shuffled to 1. The registers were also shuffled:
8008 bits 8080
A 000 B
B 001 C
C 010 D
D 011 E
E 100 H
H 101 L
L 110 (HL)
(HL) 111 A
Datapoint did not want Intel's future processors to be able to execute Datapoint machine code. They had a lot invested in their software.
Datapoint also had a 5500 processor which was more powerful than the 2200. It was microprogrammed rather than the simpler logic decode of the 2200. It was compatible with the 2200 but had many more instructions (think Z80). Yes it was that instruction set. The engineers at Intel who worked on the 5500 design left to form Zilog.
I worked as an electronics technician at Datapoint and performed test and repair of many 2200 and 5500 processor boards including writing short machine code routines to exercise the hardware.
After I left Datapoint (1977) I worked for Tandy where I repaired thousands of TRS-80 Model 1 computer boards which used the Z80. When the Tandy engineers came into the repair area with the programmers who had written Level 2 BASIC for the TRS-80 with the first masked ROMs, they tried the ROMs on a board and it didn't work. I told them that all the boards in the area needed repair but I had one that I had just repaired. I was introduced to Bill Gates and Paul Allen and the ROMs were put on my repaired board. I typed in a one line program to count and print numbers on the screen and it worked. Bill Gates offered me a job at Microsoft which had about a dozen employees but I turned him down and stayed at Tandy. I wrote more test programs and transitioned into full-time programming.
I tried getting friends to play RPG's in the early 1980's but they didn't show much interest until I came across a supply of 6" (150 mm) square pieces of styrofoam (discarded packing material from work) which I painted with gray acrylic paint. I cut some in half and some in quarters and used them to depict the dungeons for use with metal miniatures. After that I had a group which showed up every month for 5 years.
I wrote a program for my computer which generated dice rolls, monsters, treasures, and random names to assist me in my role as Dungeon Master but the critical element was my ability to ignore or re-roll any result which seemed too unfavorable. Good players really help the game but a good Dungeon Master is essential for an enjoyable game. Computers alone cannot exhibit the empathy necessary for a great game.
This is very interesting but does not appear to be helpful for the development of my TTA processor design. It appears that this project aims for more parallelism similar to VLIW than my simple MOVE architecture targets.
I would very much appreciate feedback and suggestions regarding my preliminary specifications which will be changing in the near future (before year's end) to include MUL, DIV, and floating point support. I really want to have a firm specification before proceeding with the VHDL implementation.
I always log out. I cannot think of any advantage to remaining logged in. I can easily envision disadvantages to remaining logged in whether those reasons are real or imaginary. I also lock the door to my apartment when I leave. There are people who will take advantage of any opportunity they find.
When I worked for a company that made label printers we had a potential customer who wanted us to print labels with human readable and barcode fields with 4 random letters and 4 random digits but did not want the letters to spell any obscene words. We asked for a list of words to ban but they declined to provide such a list. We did not get the contract.
I see one of the advantages being that it is very easy to learn due to its simplicity. There is also no need for complex instruction decoding placed on the hardware designer.
For software there may be a slight increase in complexity for control flow because it is necessary to specify the addresses where execution continues both when the condition is met and when it fails versus CISC which specifies only the address to branch to when the condition is met and defaults to the next instruction inline when it fails but there is also a gain in flexibility by specifying both addresses because you could, for example, call one subroutine for Z and call another subroutine for NZ and both would return to the next instruction inline.
When I first read about Move machines it appeared that they were very inefficient and the simple ones described were. In the decades since then I have devised means to offset that inefficiency with more powerful hardware functions. Especially with an FPGA target it is possible to perform complex functions in hardware that only needs to be memory mapped. Depending on your application you could have vector math, complex number math, or SIMD instructions which run in a single machine cycle. It is possible to have a shift-and-add multiplier which takes several cycles that can be loaded then you could perform some other operations while waiting for completion. I have written shift-and-add multiply routines for microprocessors which needed the processor to do the shifts and to do the adds which kept it fully occupied. While I do not claim that the design I have documented is the optimal processor, I maintain that it should have reasonable performance.
One of my goals in releasing this design is to draw interest and receive suggestions and recommendations for improving it from the highly intelligent community that reads HN and uses Github. I would like to see it optimized.
Thanks for this link. I will read it when I have time.
I currently have an accumulator at an address.
Moving to the next address ANDs with the accumulator.
Moving to the following address ORs with the accumulator.
Subsequent addresses XOR, ADD, ADC, SUB, SBB with the accumulator.
I have a location called Z and one called NZ which may be written. Reading from either location returns what was written to Z if the Z flag is set, otherwise both read what was written to NZ. Moving either to the PC effects a conditional JUMP. Moving either to the relative register adds it to the PC (relative conditional Jump). Moving either to the Indirect register pushes the PC on the stack and writes to the PC (conditional call).
I envision the capability of using the accumulator as a floating point register and having locations which perform floating point operations in a similar manner. It could also be considered as a vector and there could be locations which perform vector operations on it.
I have a Spartan 3AN dev board, another Spartan6 board, and an Arty. I was using Xilinx ISE free version to develop for the other boards until I bought the Arty. It came with a one year license for Vivado. I did not know that activating the Vivado license locked me in to developing only for Arty. ISE will no longer synthesize for any other target. I strongly dislike the closed nature of their software licensing.
I am retired but the last 10 years I worked writing VHDL. I can kind of read Verilog and understand what it does but do not know it well enough to write in it. The systems I worked on were for oil well logging. My circuits went down a 16,800 ft. hole where it was 350° F and the pressure was over 7000 PSI. Production quantities were typically less than 100. We used no bigger an FPGA than was needed to keep power at a minimum as there was no way to dissipate heat. Also the circuit boards were quite small since they needed to fit into a housing less than 2" in diameter. Frequent design changes were needed but all ran on the same boards.
I am currently working on a processor design that I call NISC. The set of all opcodes is the null set. It's a single instruction machine that does a move instruction with two operands, Source Address and Destination Address. I have considered putting the specifications and design on the internet as open source but am not sure where I should put it. Would anybody be interested in seeing it and where do you think I should put it?
This explains some digital logic but does not actually explain how a CPU works.
It does not explain an XOR gate, but references them. It also does not explain flip-flops, but references them also.
There should probably be an explanation of state machines since they are usually used to control the cycles in a CPU.
The title is actually "How does a CPU works?" but other than these few things it was a good article.
I know that text messages seem more harsh than intended and do not wish to seem demeaning, but helpful.
I bought a book called "Thinking Machines" by Irving Adler in 1962 which explained the concepts in this article (except for the 74181 ALU) and the XOR and flip-flops but did not understand how a computer actually worked until many years later.
The method I used when I was Software Development Manager was to ask one of the programmers how long he thought it should take (or estimate it myself). Then I told management that it would take 3 times that long. We usually could make that deadline but it was often close and sometimes a little late. I have since learned that it will take PI times as long as you think.
Telling the programmers that they have half as long does no good. They will not write code any faster. It may even distress them and a distressed programmer produces less code causing it to take longer.
FYI
Consider carefully what I say; my first computer program compiled and ran in the summer of 1967. I have typed in a program while both Bill Gates and Paul Allen watched over my shoulder. I'm retired now but still work daily on a subgame for minetest.