I can tell you, as someone that had some experience in the industry with this, that the two problems are :
- Teach people new paradigms - unfortunately, not all FPGA/Asic devs are fond of OOP nor have python on their abilities
- Get further down the rabbit hole of framework debugging. To add a new layer on top of the horrible beasts that Xilinx Vivado/ISE or Intel Quartus are, one must ensure that the work is really going to be faster and more reliable.
In the end, on the most constrained workflows, one would have to verify first the python/HDL code using MyHDL, then verify the generated VHDL using the industry tools, then go through the synthesis and place and route processes, add some verification layers there then test the result.
Convincing a team to accept such a framework takes time and organization.
In the end, on the most constrained workflows, one would have to verify first the python/HDL code using MyHDL, then verify the generated VHDL using the industry tools, then go through the synthesis and place and route processes, add some verification layers there then test the result.
Convincing a team to accept such a framework takes time and organization.