> Where is the RTL? Where are the GDSII masks? Why am I unable to look at the branch predictor unit in the Github code viewer? Or (God forbid!) the USB/HDMI/GPU IP? I reject the notion that these are unreasonable questions.
As you note correctly, the ISA is open, not this CPU (or board).
The important point is that using an open ISA allows you to create your own CPU that implements it. This CPU can then be open (i.e. you providing the RTL, etc.), if you so desire
I assume it will be much more difficult (or impossible?) to provide the RTL for a CPU with an AMD64 ISA, since that one has to be licensed. I wonder if you paying for the license allows you to share your implementation with the world. Even if it does, it's less likely that you will do so, given that you will have to pay for the licensing fee and make your money back
Since there is no license to pay for in case of RISC-V, it allows you to open up the design of your CPU without you having to pay for that privilege
I agree! Science is about experiments to verify hypotheses. Design of Experiments seems like a fundamental part of that. That's also why the quote below made me laugh.
> What if you don’t care about efficiency or causality?
"Yeah, what about if you don't care about money/time and are happy with finding a correlation only?!!?"
I like the idea of Gemini and was inspired to write a script to turn my blog posts written in markdown to gemtext. Sadly I still haven't finished that script ...
My main issue with the protocol is that it is requiring creating a new TLS connection for every request. That is indeed a simple approach but I argue that the extra round trip times added due to this are not worth the trade-off for the simplicity gained in this case
Coming up with a simple way to reuse a connection would reduce the round trips needed drastically. If we put our heads together, I feel like we could come up with a way to do that, that doesn't overly complicate the protocol ...
I have only just started out but it feels nice indeed! A hindrance is that I am not very artistically gifted, but as long as I make it mostly for myself, I don't mind too much.
Hm, I am using [dwm](https://dwm.suckless.org/) with a custom keybinding to shift to the left or right workspace. That seems similar enough, other than the fact that changing the split ratio will affect all workspaces on dwm while on Niri it most likely will not ...
In general, I think having ligatures in a monospace fonts is a bad idea.
The reason is that in a monospaced font all the glyphs are supposed to the same advance value. This forces the ligatures to always take up the same space as two (or however many glyphs) are involved, which may stretch the ligature glyph in a non-intended way (if it is even possible to rasterise it that way).
Monospace fonts are also often used for programming (because they make sure that the columns line up consistently, regardless of the font being used). I personally don't see the point in showing ligature glyphs that do not correspond to the actual Unicode code points encoded to bytes in the source code.
There are one or two advantages over regular GUIs, but that's it.
The biggest is probably that they are lightweight since there are no GUI library dependencies (and if there are TUI ones, they are usually much lighter than their GUI sisters). This also means there are fewer (if any) dependencies to distribute compared to a GUI.
The only other advantage I can come up with is that a TUI will have to be usable by keyboard only (in almost all cases). This is not a given for regular GUI libraries.
I'm not a fan of TUIs either. I think the only one I am using regularly is `tig` (https://jonas.github.io/tig/). I guess the reason is that I don't have to remember the git revision list syntax that way and that `tig` allows for easy commit searching with `/` ...
As you note correctly, the ISA is open, not this CPU (or board).
The important point is that using an open ISA allows you to create your own CPU that implements it. This CPU can then be open (i.e. you providing the RTL, etc.), if you so desire
I assume it will be much more difficult (or impossible?) to provide the RTL for a CPU with an AMD64 ISA, since that one has to be licensed. I wonder if you paying for the license allows you to share your implementation with the world. Even if it does, it's less likely that you will do so, given that you will have to pay for the licensing fee and make your money back
Since there is no license to pay for in case of RISC-V, it allows you to open up the design of your CPU without you having to pay for that privilege