eaasen · HackerTrans

FWIW, we had to have the idle speed of our fans lowered because the usual idle of around 5k RPM was WAY too much cooling. We generally run our fans at around 2.5kRPM (barely above idle). This is due to not only the larger fans, but also the fact that we optimized and prioritized as little restriction on airflow as possible. If you’ve taken apart a current gen 1U/2U server and then compare that to how little our airflow is restricted and how little our fans have to work, the 12X reduction becomes a bit clearer.

eaasen

2 anni fadiscuss

We do not put the onus on customers to tolerate data loss. Our storage is redundant and spread through the rack so that if you lose drives or even an entire computer, your data is still safe. https://oxide.computer/product/storage

eaasen

2 anni fadiscuss

This is how our rack works (Oxide employee). In each power shelf, there are 6 power supplies and only 5 need to be functional to run at full load. If you want even more redundancy, you can use both power shelves with independent power feeds to each so even if you lose a feed, the rack still has 5+1 redundant power supplies.

eaasen

3 anni fadiscuss

It’s certainly possible someone did a BOM substitution and didn’t due diligence on it, but I doubt it. PCB assembly houses tend to notice components that are suddenly too big for their pads because they’ll have fallout in AOI or later testing.

The underfill was likely added before full production as the result of reliability tests that showed some mechanical susceptibility of that IC.

eaasen

3 anni fadiscuss

As someone who designs circuit boards professionally, the explanation is clearly lacking. There might be a thermal issue or there might not be. There is nothing conclusive in the pictures either way. What I do see is the following:

1. Underfill (the brownish-tan smooth material surrounding the components towards the bottom of the picture) around the IC, which is typically done to make parts more mechanically robust.

2. No evidence of overheating on any of the thermal interface material that is left stuck to most of the components and no evidence of overheating on the PCB or the components themselves.

3. Completely insufficient evidence to declare a soldering issue. The way to prove this one way or another is x-ray inspection to look for voids in the solder or a mechanical cross-section of the suspect solder joints.

While this certainly could actually be the problem, I see insufficient evidence to conclude one way or another. Manufacturers don’t put underfill under a part unless it’s required through testing or experience with similar package types in prior designs since it adds cost, additional process steps and makes it a PITA or impossible to rework any bad components in the area.

As to the pad size/shape, there are three general classes of design defined by the IPC (standards body that deals with PCBs and PCB assemblies). Depending on how space constrained your design is, there are different recommended pad designs for passive components like these. They might be using one of the tighter spacing guidelines, but if their process is well controlled, it can be perfectly fine for the design life of the product.

If you want to see small pad layouts done well, look at an iPhone logic board.

If you want to know more about pad design for SMT parts, search for IPC-7352

eaasen

3 anni fadiscuss

The NIC is a chip-down Chelsio T6 ASIC with 2x100GbE ports, one going to each Ethernet switch in the rack.

eaasen

3 anni fadiscuss

My apologies, this was not intended to be inflammatory but the quotes out of the article and the comments were raised to point out that these kinds of baseless and biased comments from the author detract from the objective quality of the information previously presented in the article and lower the credibility of the author and even the information that the author presents.

eaasen

3 anni fadiscuss

[flagged]

eaasen

4 anni fadiscuss

Timing adjustment per x number of data bits has been required since DDR3 but DDR4 also has internal reference voltage calibration for DQ bits (VREF_DQ). This voltage sets threshold by which the IO cell determines if a voltage represents a logic high or low. This VREF_DQ value is calibrated per x number of bits in addition to adjusting the timing to try to find the best place to sample the signal.

eaasen

4 anni fadiscuss

The regulators are actually quite sophisticated and have many undocumented registers that set how things like the communications with the processor work, nonlinear control algorithms, etc.