victor82

  class Euler(Elaboratable):
    def __init__(self):
        self.output = Signal(19)

    def elaborate(self, platform):
        m = Module()

        count5 = Signal(3)
        c3, c5 = Signal(17), Signal(18)

        cond3, cond5 = (c3 < 1000) & (count5 != 0), (c5 < 1000) & (count5 < 3)

        m.d.sync += count5.eq(Mux(count5 == 4, 0, count5+1))
        m.d.sync += [
            c3.eq(c3+3),
            c5.eq(Mux(cond5, c5+5, c5))
        ]
        m.d.sync += self.output.eq(self.output +
                                   Mux(cond3, c3, 0)+Mux(cond5, c5, 0))
        return m

  Location: Chile
  Remote: Yes
  Willing to relocate: Could be, depends on the place and project
  Technologies: C, Golang, Python, VHDL, Verilog, Amaranth HDL, FPGAs
  Résumé/CV: https://www.linkedin.com/in/victor-mu%C3%B1oz-79955093/
  Email: victor at avoid dot contact
  Github: https://github.com/vmunoz82