The insults were justified given that you ignored my emails until I resorted to spamming your inbox twelve hours in.
Here's my email because I have nothing to hide:
>Hey,
Could you clarify why did you shadow ban my account, or am I just breaking your circlejerk by posting opinions your mods disagree with?
Also how are my posts related to IC design flagged as dead?Literally every other comment that is slightly political being removed I'd understand but apparently your moderators are just mentally insane.
Can you also explain why you harbor AI-made garbage on site? Doesn't help the website's "Quality".
Not only that, but 180nm/130nm is the only option that is OpenSourced, as of now.
Transistor Libraries for ICs (or, PDKs) have long been proprietary. I'm only aware of IHP and Sky130, which are actually banking on Fossi or Libre Silicon design.
As a person that is using Librelane daily in their workflow, why did they skip Gate-level simulation? Iverilog won't ensure the circuit works after tapeout, CVC most likely will.
SDF-annotated simulation actually shows data hazards, as well as transistor timings.
So they treat their corporate customers the same way they treat devs or consumers on their forums?
Lmao. Shifting responsibility is real.
"Actually it is YOUR problem that we broke something*