Show HN: Fast VHDL language server written in Rust(github.com)
github.com
Show HN: Fast VHDL language server written in Rust
https://github.com/VHDL-LS/rust_hdl
5 comments
One thing that makes it so fast is the multi-core analysis of the code. Internally it parses every file in parallel since at the parsing stage there are no dependencies. When it comes to semantic analysis of the code it will compute the dependency tree and analyze it in parallel while also detecting circular dependencies.
The declarations in each design unit are allocated in their own arena allocator. The declarations in one design unit can link to other design units and even create circular references for implicit functions which usually reference the parent type. The reference are direct without having to use the atomic reference counted type Arc. This is because the units are analyzed in dependency order and a dependent unit gets a read-only view of the arena of its dependencies to create direct references.
When the user types in the editor the language server will invalidate the modified design unit and any dependencies and just re-analyze those so it is even faster when used interactively then when starting up the first time. Since invalidating a design unit invalidates all dependencies the segmented arena structure described above cannot create dangling pointers.
The declarations in each design unit are allocated in their own arena allocator. The declarations in one design unit can link to other design units and even create circular references for implicit functions which usually reference the parent type. The reference are direct without having to use the atomic reference counted type Arc. This is because the units are analyzed in dependency order and a dependent unit gets a read-only view of the arena of its dependencies to create direct references.
When the user types in the editor the language server will invalidate the modified design unit and any dependencies and just re-analyze those so it is even faster when used interactively then when starting up the first time. Since invalidating a design unit invalidates all dependencies the segmented arena structure described above cannot create dangling pointers.
I have been using this for the past few weeks for my thesis in Emacs & VS Code and have loved it! Thank you so much. Writing in a design suite was a really annoying process.
In the scope of my thesis I have to generate a lot of documentation, and I've been looking into parsers whose AST I can use to help automatically generate this. Would this be possible with vhdl_lang, if comments have been added? I currently have a Python script that regexes its way through with a lot of edge cases, but this is not a reliable way of doing it if I want to add more features.
In the scope of my thesis I have to generate a lot of documentation, and I've been looking into parsers whose AST I can use to help automatically generate this. Would this be possible with vhdl_lang, if comments have been added? I currently have a Python script that regexes its way through with a lot of edge cases, but this is not a reliable way of doing it if I want to add more features.
It depends on what you mean by possible. The vhdl_lang crate solves many hard problems required to do document generation such as parsing, disambiguation and connecting references. It solves it in a much more complete and better way then a regex ever could.
So vhdl_lang is a good base for a document generator but it does not implement one today. My hope with this project was to create a generic VHDL language backend that others could build tools upon instead of reinventing the wheel. I myself have focused on the language server and core library itself and not on document generation.
So vhdl_lang is a good base for a document generator but it does not implement one today. My hope with this project was to create a generic VHDL language backend that others could build tools upon instead of reinventing the wheel. I myself have focused on the language server and core library itself and not on document generation.
The performance is great, it can load 200k lines in 200ms using all 8-cores on my desktop. When loaded it only consumes 220 MB of RAM.
It supports goto/find-references as well as type checking for close to all of VHDL-2008.