Intel 3 Represents an Intel Foundry Milestone(eetimes.com)
eetimes.com
Intel 3 Represents an Intel Foundry Milestone
https://www.eetimes.com/intel-3-represents-an-intel-foundry-milestone/
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> While the Intel 3 does build on the Intel 4 process, the enhancements are significant and results in a 15% improvement in front-end ring oscillator performance, a 20% reduction in overlap capacitance, a 25% reduction in contact line resistance, a 5× reduction in leakage at the same drive current, and an overall increase of up to 18% performance efficiency at the same power over Intel 4, which achieved a 20% increase in performance efficiency over Intel 7. Intel 3 can achieve these performance gains while also enabling 3D packaging, analog devices, and even higher performance products for AI and HPC.
> What Intel accomplished was a major process node transition from Intel 4 to Intel 3 in less than a year with the next two processes nodes, Intel 20A and Intel 18A, scheduled to enter production by the end of 2024.
This is quite hard for a layperson to follow, am I correct that the process sequence is:
Intel 7 -> Intel -> 4 -> Intel 3 -> Intel 20A -> Intel 18A -> ?
Is there logic to the naming?
> What Intel accomplished was a major process node transition from Intel 4 to Intel 3 in less than a year with the next two processes nodes, Intel 20A and Intel 18A, scheduled to enter production by the end of 2024.
This is quite hard for a layperson to follow, am I correct that the process sequence is:
Intel 7 -> Intel -> 4 -> Intel 3 -> Intel 20A -> Intel 18A -> ?
Is there logic to the naming?
They're trying to market themselves as a closer number to the node width, they were annoyed that 14nm by Intels metrics was marketed as 10nm by TSMC.
Which I think is ironic as AMD has been more accurately reporting TDP (Intels measurement of that metric is their expected average, where AMDs is actually peak).
I think they're scared about what happens when we get passed nanometers, even though they're not claiming nanometers it's clear thats what they're trying to evoke, and they're assuming they can go smaller, so that's where the "A"s (meant to closely resemble "Angstrom" without actually saying it) come from.
Which I think is ironic as AMD has been more accurately reporting TDP (Intels measurement of that metric is their expected average, where AMDs is actually peak).
I think they're scared about what happens when we get passed nanometers, even though they're not claiming nanometers it's clear thats what they're trying to evoke, and they're assuming they can go smaller, so that's where the "A"s (meant to closely resemble "Angstrom" without actually saying it) come from.
The 18A naming convention is as simple as not wanting to put a decimal point in their node name. Simple as that. It's not like the the "nanometer" node names actually mean anything at this point anyways. Neither TSMC N3 or Intel 3 have any dimension in their transistors which are 3nm. I would be very unsurpassed to see other foundries copy the convention, it's a lot cleaner.
They're not meant to be understood by the layperson since they're not actual nm or angstrom numbers but just marketing numbers based on some internal feature sizes.
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The next CMOS processes that are being developed by Intel, i.e. 20A, 18A and 14A will be considerably different, by making transistors where the gate surrounds completely the channel.
Only after Intel does that successfully they can claim to have reached again parity with the best at CMOS manufacturing.
It is not clear whether the first such process, 20A, is still intended to be used for any commercial product.
When 20A was first announced, it was said that it will be used to manufacture Arrow Lake, starting in the second half of this year.
Meanwhile, Intel has decided to retarget Lunar Lake (Q3 2024), Arrow Lake S (Q4 2024) and Arrow Lake (Q1 2025) to some "3 nm" TSMC processes, outsourcing thus their production.
The successor of Arrow Lake and Lunar Lake, Panther Lake (H2 2025) is said to use the 18A CMOS process, bringing back to Intel the production of consumer CPUs.
This may mean that the 20A CMOS process will be skipped completely for commercial products, after being used only for batches of test chips, needed to develop the new technology, which is the basis for the improved 18A and 14A processes.