I implemented Multi-protocol audio transmitter that repurposes the Parallel IO peripheral on the ESP32-P4 to synthesize digital audio output signals, clocked by the APLL for sample-accurate timing.
We chain three peripherals together in ways they were never designed for:
Peripheral 1 -- APLL: Generates a precise audio master clock. Standard audio frequencies (12.288 MHz for 48 kHz, 11.2896 MHz for 44.1 kHz) are native to this PLL.
Peripheral 2 -- I2S: Misused purely as a clock conduit. We allocate an I2S TX channel, configure it with I2S_CLK_SRC_APLL, but never write audio data to it. Its only job is to output MCLK on a GPIO pin. The I2S BCLK/WS/DOUT pins are left disconnected (or optionally used for real audio output as a "free" bonus).
Peripheral 3 -- PARLIO: Designed for parallel display interfaces (LCD, LED matrices). We repurpose it as a multi-channel I2S transmitter. It reads the MCLK from the GPIO (via the GPIO matrix), divides it down to BCLK, and shifts out pre-computed bit patterns from DMA buffers on every BCLK cycle.
This way we can get upto 304 channels and rates like 192kHz without a lot of CPU involvement.
In the future, when ESP-IDF implements the PARLIO RX mode, we will implement also receiving. Also, the Bitscrambler Peripheral could be used to encode data for S/PDIF and ADAT outputs.
We chain three peripherals together in ways they were never designed for:
Peripheral 1 -- APLL: Generates a precise audio master clock. Standard audio frequencies (12.288 MHz for 48 kHz, 11.2896 MHz for 44.1 kHz) are native to this PLL.
Peripheral 2 -- I2S: Misused purely as a clock conduit. We allocate an I2S TX channel, configure it with I2S_CLK_SRC_APLL, but never write audio data to it. Its only job is to output MCLK on a GPIO pin. The I2S BCLK/WS/DOUT pins are left disconnected (or optionally used for real audio output as a "free" bonus).
Peripheral 3 -- PARLIO: Designed for parallel display interfaces (LCD, LED matrices). We repurpose it as a multi-channel I2S transmitter. It reads the MCLK from the GPIO (via the GPIO matrix), divides it down to BCLK, and shifts out pre-computed bit patterns from DMA buffers on every BCLK cycle.
This way we can get upto 304 channels and rates like 192kHz without a lot of CPU involvement.
In the future, when ESP-IDF implements the PARLIO RX mode, we will implement also receiving. Also, the Bitscrambler Peripheral could be used to encode data for S/PDIF and ADAT outputs.