Author here. I did overclock it - that was one of the points of the writeup: when you modify the memory clock, you should change the timings along with, because they are often specified in tCK (ticks of the memory clock), and as such, they will change when the clock changes.
I have reliable information from folks with several thousand of these FPGAs that they reliably clock to 1100Mhz - 1150Mhz on the HBM2 at stock voltage (or a bit less.) This falls in line with my personal experiences - I have seven XCVU35P FPGAs, and they range from doing only 1100Mhz to 1150Mhz, to some handling 1200Mhz.
Samsung's documentation specifies this HBM2 for 1000Mhz to 1100Mhz, based on binning - this is why I was annoyed that Xilinx limited it to 900Mhz, and worked to learn how to change the PLL settings.