Yes, except the important parts. In Moore’s law scaling, you reduce the cost per transistor, and because of that there is money for capex and the consumer benefits.
In Huangs law, si is commoditized, so the benefit accrues to the designer and software makers, and really only in narrow domains.
Dennards law held until the approximately linear relations that made it work ended. Delay stopped being entirely gage, and more importantly, voltage couldn’t drop forever, due to material limits and intrinsic silicon limits.
Has nice models and details on post cmos, for the curious. The papers (nikonov and young) are excellent, though I think they underrate the back end scaling challenges.
This is about replacing the low k dielectric in the backend, and makes sense if you consider that backend metal will move to W or Co. so long as this is CMP capable (maybe?) this makes sense.
Well said. I will add that each different industry is different, and often every company aligns the role somewhat differently.
If you are building enterprise software, vs hardware, vs consumer products...the process can be very different, with different balances on risk and very different timelines
This is just....not true. IBM doesn’t make 5nm chips. This is a research demo of a transistor design for that node. They don’t make it, and never will.
I can split any small pitch exposure into separate, larger pitch exposures. For instance, if I need 40nm pitch, and my system is limited to 80nm, I can do 4 exposures. The next shrink requires 8.
To figure this out, draw a square, and each node is an exposure.
This process works forever in theory, but is limited in practice by the mutual registration of the exposures.
In Huangs law, si is commoditized, so the benefit accrues to the designer and software makers, and really only in narrow domains.