Imec demonstrates logic and DRAM structures using High NA EUV Lithography(imec-int.com)
imec-int.com
Imec demonstrates logic and DRAM structures using High NA EUV Lithography
https://www.imec-int.com/en/press/imec-demonstrates-logic-and-dram-structures-using-high-na-euv-lithography
15 comments
Can someone add some context here? What does this translate to for the future of semiconductor tech?
The hope is these machines will reduce the number of steps to produce advanced chips (<3nm logic and DRAM), and hopefully the time and money cost of production will be lower compated to the current lithography techniques. A lot of people are still skeptical because of the cost of the machines, the potential low yield, high energy consumption etc.. So we need to see till fabs adopt this (if ever) and if it's the way to go.
If this turns out to be a dead end it'll be a big problem for ASML at the first instance. Also it's going to be good news for China since the technology gap will not be opening further.
If this turns out to be a dead end it'll be a big problem for ASML at the first instance. Also it's going to be good news for China since the technology gap will not be opening further.
If this turns out to be a dead end, Intel will be in even deeper shit. They've been buying up all of ASML's High NA machines before the technique has been completely proven. It's a bold move.
Last I heard, Microsoft already has designs that it wants to fab on 18A.
At the end of the day it'll come down to how much and how fast 18A can help recoup what they're spending right now.
At the end of the day it'll come down to how much and how fast 18A can help recoup what they're spending right now.
I don't think they will last that long. TSMC could bring 7nm, 5nm and 3nm to market because Apple just straight out funded these processes with agreements to buy the capacity exclusively for the first year or so. Even Nvidia couldn't access it till now (if I didn't miss it). Companies are interested in 18A as a second supplier, mainly to increase capacity on advanced nodes. This though requires everything to go better than the plan. Intel wasn't a foundry for others, so they don't have the experience to support different companies needs (from design flow to IP availability like standard cells, ESD, Serdes etc). TSMC doesn't only develop a process but develop all the stuff around it to serve a diverse set of customers. Now, if Intel gets 18A right it's great. It doesn't mean everyone jump on it and book huge amounts of capacity. If the design fliw isn't streamlined and it takes too long to tape-out adoption will not be there. Global Founderies 14nm and 12nm are great examples of this.
Intel is all-in on High NA EUV to try and regain the lead. TSMC and Samsung also have plans for High NA, but not as aggressive, because High NA is not a proven technology, but it will be required to prevent Moore's Law from grinding to a complete halt.
IMEC has just taken steps to prove that High NA can work. They are a European semiconductor R&D company; they don't operate any commercial fabs of their own.
IMEC has just taken steps to prove that High NA can work. They are a European semiconductor R&D company; they don't operate any commercial fabs of their own.
NA is numerical aperture and physically relates (by the uncertainty principle) to the attainable resolution of an imaging system. Resolution scales linearly with NA and inversely linearly with wavelength. High NA EUV means EUV scanners with a higher NA so higher resolving power than the current generation. The "normal NA" for EUV is 0.33. High NA means 0.55. (These are EUV marketing terms; ArF immersion tools went to NA 1.35, but using 15x longer wavelengths).
The economic significance is that current leading edge processes have to use multiple patterning with normal NA machines to achieve the necessary resolution. Multiple patterning means multiple exposures with different masks on the same spot creating interference patterns. This halves / quarters etc. throughput and decreases yields (every exposure needs to be flawless).
High NA means you just need one exposure and mask (per layer).
The economic significance is that current leading edge processes have to use multiple patterning with normal NA machines to achieve the necessary resolution. Multiple patterning means multiple exposures with different masks on the same spot creating interference patterns. This halves / quarters etc. throughput and decreases yields (every exposure needs to be flawless).
High NA means you just need one exposure and mask (per layer).
Until they start to do multiple exposures with this high NA to achieve even more next year
That's the traditional course of action. As long as it's financially sound they will at least try it.
At that point making smaller patterns might not be the biggest issue. Vias are becoming s bottleneck and proven to be hard to scale down. If we cannot fibd a new way to open vias reliably and with low resistence it will be bottleneck for scaling down.
At that point making smaller patterns might not be the biggest issue. Vias are becoming s bottleneck and proven to be hard to scale down. If we cannot fibd a new way to open vias reliably and with low resistence it will be bottleneck for scaling down.
Yeah but then it's a bit the end of the road, since there are no workable refractive media for EUV, not even on paper, which categorically rules out higher NA optics, which was half the reason for why ArF was able to be used for about 20 years.
High NA EUV is the next generation of EUV machine that is able to make features that are approximately 50% smaller than regular EUV. As such, this roughly means higher capacity RAM (this will probably go into production sometime around DDR6 or DDR7)
On the consumer side? Higher capacity RAM comes to mind.
What I'd be more interested in is, does this also mean bigger/denser L1-L3 caches?
What I'd be more interested in is, does this also mean bigger/denser L1-L3 caches?
> What I'd be more interested in is, does this also mean bigger/denser L1-L3 caches?
Just a semi-engineer here, not a semi-conductor engineer, but probably not. L1-L3 are on the die, so you'd just be making those at the same time as the rest of your CPU die, so they'll be made with the same process as that is. Which, once that process is the high NA UV, means yes, denser L1-L3. Though I wouldn't be too surprised to see an L3/L4 chiplet made with an older process for low-end CPUs... which might mean smaller cache?
Just a semi-engineer here, not a semi-conductor engineer, but probably not. L1-L3 are on the die, so you'd just be making those at the same time as the rest of your CPU die, so they'll be made with the same process as that is. Which, once that process is the high NA UV, means yes, denser L1-L3. Though I wouldn't be too surprised to see an L3/L4 chiplet made with an older process for low-end CPUs... which might mean smaller cache?
The more important reason this doesn't mean denser caches is that the caches are SRAM not DRAM which are petty much completely different processes. High NA EUV also will likely yield higher density caches, but this is mostly unrelated.
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