It is interesting that one can write code (for which certain computational/logic structures are automatically inferred) describing hardware to run inference models, while inferring that such a piece of computing power will be useful to infer the future.
No hardware: no software. Nobody wrote Google until cheap servers were available, and nobody made antibody treatments for cancer until cheap protein synthesis became available. This paper is cute and fun but ultimately worthless intellectual masturbation.
> the simplest action for a chip on the SPI bus would be to hold the MISO line low during power on
MISO is master-in, slave-out for anyone not familiar with serial peripheral interface jargon. Usually, the slave quad-SPI memory would send the configuration over this line, so pulling it low should dump the real data to ground.