The equipment in chip fabs is highly sensitive to weather and natural disasters. So sites like Arizona, Austin, Oregon are chosen due to low prevalence of earthquakes no hurricanes etc.
The fabs anyways don’t ship chips to the devices they go into, they do to a separate site where they get tested, packaged and then are sent off.
The reason to onshore this is not about scale but process capability and adding security to supply chain in case Taiwan gets in a conflict. It’s not about scale but ability to produce high yielding chips at shrinking technology size, is vastly becoming a physics problem at smaller nodes.
Reality is that Samsung and Intel could run a similar fab but their yields, efficiency and process development is lagging behind TSMC. So easier to onshore TSMC process here that help Intel learn how to speedrun transition to foundry model (producing others chip designs)
Off topic but how awesome is it NPR has a text only version? What a mess the internet is that basic getting news requires checking off 3 privacy requests, newsletter asks and ads littering the story
Is anyone else using blink and vsCode for this? Seems like really good tool, but I am not sure how to turn off the smart quotes “”. Is this AVP that’s enabling, this or a vsCode/blink setting I need to resolve
Very cool. If you like the idea of a pocket synth but want something more powerful, the dirtywave m8 is a fantastic full featured tracker, with multiple synthesis models, stereo sampling, I/O and ability to send audio over usb.
I went vegetarian last year because of this. I probably ate 1 lb of meat a day before and I loved meat. I went towards vegetarian first as I wanted to make the habit stick then as I learn more vegan cooking can make the change to veganism. It was about 9 months ago and it has been the easiest change in my life
One aspect is meeting the overlay and CD targets throughout the stack to meet yield. Having a process that can find defects and more importantly practices to minimize the defects in your process is a big piece. Typically the process given to mass production would be only half solved and then the fab is trying to refine it in ramp.
I used to manage a fab of high end ASML tools and there is a non trivial list of things to continue and solve. You have reliability issues that require scheduling long (2-5 weeks) downtime to fix.
An upstream defectively issue in a spinner tool might lead to taking one dispense or develop node out of flow to improve the defect rate but in turn tank the Scanner efficiency by 40% as it waits to output wafers and that backs up the imaging. The reality is the ASML tools given to fans don’t have everything ironed out at rhe start. So fabs see the reliability issues in real time but there’s no time for the fab to take it out of production for 3 months to address a major part replacement. These all lead managers to make bad choices that continue to dig you in a hole.
At the time I was supporting 14nm it was well known TSMC had world class software tools and practices to minimize their fabs defects and maximize higher order control of overlay and CD bias. This allows them greater flexibility to take a tool down and fix the issues rather than live with them or have to use a band aid.
EdiT: I did not work at intel so can only speculate why they are behind but it was also well known TSMC photo engineers were worked 80+ hrs/week always . They were paid less so they hired more of them and they worked a lot longer so as a result they had better fab processes and support tools.
The fabs anyways don’t ship chips to the devices they go into, they do to a separate site where they get tested, packaged and then are sent off.
The reason to onshore this is not about scale but process capability and adding security to supply chain in case Taiwan gets in a conflict. It’s not about scale but ability to produce high yielding chips at shrinking technology size, is vastly becoming a physics problem at smaller nodes.
Reality is that Samsung and Intel could run a similar fab but their yields, efficiency and process development is lagging behind TSMC. So easier to onshore TSMC process here that help Intel learn how to speedrun transition to foundry model (producing others chip designs)