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mshockwave

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RISC-V Vector Primer

github.com
4 points·by mshockwave·5 miesięcy temu·0 comments

Machine Scheduler in LLVM – Part II

myhsu.xyz
31 points·by mshockwave·8 miesięcy temu·0 comments

Machine Scheduler in LLVM

myhsu.xyz
1 points·by mshockwave·10 miesięcy temu·0 comments

comments

mshockwave
·16 dni temu·discuss
one of the reasons I rarely read press releases is that I don't believe in promises -- I believe in _incentives_. In this case, what will Qualcomm be incentivized to do? What are in their interests?
mshockwave
·16 dni temu·discuss
indeed, open sourcing is only half (or even less) of the picture: who is driving the open source community and how it is driven (i.e. governing structure) are probably more important IMHO. There are countless of cases where an open source project is either killed by slow death, or dictated by a single entity. Chris's previous projects like LLVM and MLIR are fortunate enough to grow and thrive organically, and that takes years if not decades to cultivate
mshockwave
·2 miesiące temu·discuss
it's a book excerpt
mshockwave
·2 miesiące temu·discuss
> Does gcc use LLVM anywhere under the hood

No
mshockwave
·3 miesiące temu·discuss
One thing I observed is that RVV code is usually slower in QEMU
mshockwave
·4 miesiące temu·discuss
LLVM now has another way to implement RTTI using the `CastInfo` trait instead of `classof`: https://llvm.org/doxygen/structllvm_1_1CastInfo.html

But it's really just an implementation difference, the idea is still to have a lightweight RTTI.
mshockwave
·5 miesięcy temu·discuss
how did it do regalloc before instruction selection? How do you select the correct register class without knowing which instruction you're gonna use?
mshockwave
·6 miesięcy temu·discuss
> I don’t know many good reasons for extrusive linked lists

for one, its iterator won't be invalidated
mshockwave
·8 miesięcy temu·discuss
Is it normal to spend 10minutes on tuning nowadays? Do we need to spend another 10 minutes upon changing the code?
mshockwave
·8 miesięcy temu·discuss
It's likely that Swift compiler is using LLVM LIT (https://llvm.org/docs/CommandGuide/lit.html), which is implemented in python, as the test driver
mshockwave
·9 miesięcy temu·discuss
> In the end, programs will want probably to stay conservative and will implement only the core ISA

Unlikely, as pointed out in sibling comments the core ISA is too limited. What might prevail is profiles, specifically profiles for application processors like RVA22U64 and RVA23U64, which the latter one makes a lot more sense IMHO.
mshockwave
·10 miesięcy temu·discuss
yes, it has been done for at least a decade if not more

> Even more of a wild idea is to pair up two cores and have them work together this way

I don't think that'll be profitable, because...

> When you have a core that would have been idle anyway

...you'll just schedule in another process. Modern OS rarely runs short on available tasks to run
mshockwave
·10 miesięcy temu·discuss
The article is easy to follow but I think the author missed the e point: branchless programming (a subset of the more known constant time programming) is almost exclusively used in cryptography only nowadays. As shown by the benchmarks in the article, modern branch predictors can easily achieve over 95% if not 99% precision since like a decade ago
mshockwave
·10 miesięcy temu·discuss
yes, the short answer is LLVM uses RegPressureTracker (https://llvm.org/doxygen/classllvm_1_1RegPressureTracker.htm...) to do all those calculations. Slightly longer answer: I should probably be a little more specific that in most cases, Machine Scheduler cares more about register pressure _delta_ caused by a single instruction, either traverses from bottom-up or top-down. In which case it's easier to make an estimation when some of other instructions are not scheduled yet.