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dvas

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Apple Vision Pro brings a new era of spatial computing to business

apple.com
9 points·by dvas·há 2 anos·11 comments

Logical Tensor Indexing for SPMD Programming

cs.cornell.edu
2 points·by dvas·há 2 anos·0 comments

comments

dvas
·há 2 anos·discuss
There are many ways of thinking and reasoning about the profession and what it means to each and every one of us.

Some of the buckets:

* The builders, don't care how they get the result.

* The crafters, those who care how they get to the results (vim vs emacs), and folks who enjoy looking at tiny tiny details deep in the stack.

* The get-it-done people, using standard IDE tools, stick with them, and it's a strict 9-5.

...

And many with types, and subtypes of each ^^.

In my opinion, many people have a passion for making computers to do cool things. Along the way, some of us have fallen into the mentality of using a particular tool or way of doing things and get stuck in our ways.

I think it's another tool that you must know how to utilize and utilize in a way that does not atrophy your skills in the long run. I personally use it for learning and allowing me to get an in on a knowledge topic which I can then pull on and verify that the information is correct.
dvas
·há 2 anos·discuss
Might not be for everyone, but using git to index markdown notes + linking it against cloud storage like dropbox/icloud to have it available on phones/tables have served me well over the last 5 years.
dvas
·há 2 anos·discuss
I think the best approach to take with personal knowledge bases or any knowledge data, is to have the ability to bring your data in and out as one pleases.

In my flow, I use a hybrid Zettelkasten-based approach to linking notes. vscode, zettlr, logseq, obsidian all render correctly. I am happy to see more tools which exhibit more of this "bring your own data" mantra.
dvas
·há 2 anos·discuss
I would like to add the thought of looking at where these elliptic curves are deployed, things like embedded devices and implementations bitcoin-core libraries for say secp256k1 [0].

Ref:

[0] Optimized C library for EC operations on curve secp256k1

https://github.com/bitcoin-core/secp256k1
dvas
·há 2 anos·discuss
Thanks for sharing Shane, and nice to see companies engaged with the community on a technical level!
dvas
·há 2 anos·discuss
For personal use:

What works is a good plain old rss.

Delivered to my client of choice, via gui or cli. Skipping ads and clickbait articles to save me time.

With a wave of generated content flooding some automated systems, the best curation will be done by yourself by finding reliable sources to subscribe to.
dvas
·há 2 anos·discuss
I think it is so important to be able to disconnect from whatever it is that we are doing, even for a very short period of time. Go for a walk, brew a coffee or simply close your eyes and breathe.

Many times, stress is created artificially. It hurts our performance and deteriorates our ability to think.

Encountered numerous situations where work was "urgent" and would likely land a contract or sales for the company, and everyone would be a superstar if they delivered this "crunch".

After 2 months of pulling all-nighters and sleeping for 3/4 hours, we deliver the project ahead of time. Apathy begins to set in after management/decision makers keep on giving these gifts we call "crunches".

To help the company and go the extra mile is something most of us have done in the past and will possibly do in the future. However, it's like the story of the boy who cried wolf, if everything is urgent and every task is to be done NOW, then there are bigger issues at play.

Like everything in life, there is usually a limit/budget of money, time and effort. By abusing these limits and tolerances, people will lose respect for the people crying wolf and will put less effort into their work.
dvas
·há 2 anos·discuss
To go a bit deeper, while still keeping it at a very high level what changes were made between each generation:

PCIe 1.0 & PCIe 2.0:

Encoding: 8b/10b

PCIe 2.0 -> PCIe 3.0 transition:

Encoding changed from 8b/10b to 128b/130b, reducing bandwidth overhead from 20% to 1.54. Changes here in the actual PCB material to allow for higher frequencies. Like changing away from PCB material like FR-4 to something else [2].

PCIe 3.0, PCIe 4.0, PCIe 5.0:

Encoding: 128b/130b

There is plenty to dive deep on, things like:

- PCB Material for high-frequency signals (FR4 vs others?)

- Signal integrity

- Link Equalization

- Link Negotiation

Then decide which layer of PCIe to look at:

- Physical

- Data / Transmission

- Link Layer

- Transaction

A good place to read more is from the PCI-SIG FAQ section for each generation spec that explains how they managed to change the baud rate as you mentioned.

PCI-SIG, community responsible for developing and maintaining the standardized approach to peripheral component I/O data transfers.

PCIe 1.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 2.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 3.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 4.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 5.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 6.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 7.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

[0] Optimizing PCIe High-Speed Signal Transmission — Dynamic Link Equalization https://www.graniteriverlabs.com/en-us/technical-blog/pcie-d...

[1] PCIe Link Training Overview, Texas Instruments

[2] PCIe Layout and Signal Routing https://electronics.stackexchange.com/questions/327902/pcie-...
dvas
·há 2 anos·discuss
I think a quick 2-minute read on the changes around each generation gen1 -> gen4 example from 2016 will make it a bit clearer [0].

Things like packet encoding etc. Then a quick look at the signalling change of NRZ vs PAM4 in later generations.

Gen1 -> Gen5 used NRZ, PAM4 is used in PCIe6.0.

[0] Understanding Bandwidth: Back to Basics, Richard Solomon, 2016: https://www.synopsys.com/blogs/chip-design/pcie-gen1-speed-b...
dvas
·há 2 anos·discuss
Not my area at all, just passing by and wondering to the extent and how they use knowledge graphs for drug discovery.

Some time back I had a peek at AstraZeneca's GitHub [0] and got me curious. I know in genomics they try to use custom hardware to accelerate the process using FPGAs and others [1].

Curious if anyone can shed light on knowledge graph use at scale is being accelerated.

[0] AstraZeneca; Awesome Drug Discovery Knowledge Graphs https://github.com/AstraZeneca/awesome-drug-discovery-knowle...

[1] Gene sequencing accelerates with custom hardware https://www.mewburn.com/news-insights/gene-sequencing-accele...
dvas
·há 2 anos·discuss
Extra links for the no gil work for anyone else curious about this [0], [1].

[0] Multithreaded Python without the GIL https://docs.google.com/document/d/18CXhDb1ygxg-YXNBJNzfzZsD...

[1] Github repo https://github.com/colesbury/nogil
dvas
·há 2 anos·discuss
Lots of other great answers, another one I came across recently is FinGPT[0]. For backtesting there is zipline [1], but doesn't look like it's maintained anymore.

[0] FinGPT: Open-Source Financial Large Language Models https://github.com/AI4Finance-Foundation/FinGPT

[1] Zipline is a Pythonic algorithmic trading library https://github.com/quantopian/zipline
dvas
·há 3 anos·discuss
Awesome reply, and thank you for the well put together answer linking to resources and for sharing your experience.

For Cortex-A8 from [4] and the others you have linked, It makes sense to me now regarding the instruction passing data between registers, filling out the pipeline and then stalling.

Will have a peek at ARMv8/ARMv9 arch's and see what they did there regarding SVE/SVE2.
dvas
·há 3 anos·discuss
Got me curious regarding ARM latency, wonder if that was related to particular instructions which added more latency or transfers between the registers/memory subsystem internals. Also on the off-chance that you remember, did you inline intrinsics or let the compiler auto-optimize?

Interesting to test out on the ARM Mac, and see if different dependency chains show significant latency penalties / in with reorder buffer.
dvas
·há 3 anos·discuss
This is great! What a lovely read.

Reminds me back of my teenage years mesmerised by software/hardware synths, daws and everything and anything related to audio tech. Hours spent trying to understand different waves, oscillations, LFOs, modulation, AM, FM and so on and so forth. I could go on all day. Great memories.

Anyhow, would be interesting to go down a rabbit hole reading up on the waveform representation for the DX7. Now that I remember, I will go ahead and look for SH-101.
dvas
·há 3 anos·discuss
Useful when you want to have multiple git accounts changing based on the path. Thanks for the share! In my case it was changing the ssh key based on the project folder.
dvas
·há 3 anos·discuss
Enjoyed reading it! Great overview of different concepts involved while building DB's. From mentioning SIMD to squeeze out performance on a single machine all the way to consensus algorithms.

While on the topic of DB's, reliability and distributed systems. Formal methods and how they can be applied in these situations and formally apply to Database internals for anyone else wishing to read up on as another concept.

Interesting paper on the S3 team using TLA+ to model.

[0] Use of Formal Methods at Amazon Web Services https://lamport.azurewebsites.net/tla/formal-methods-amazon....

[1] How Amazon Web Services uses formal methods https://www.amazon.science/publications/how-amazon-web-servi...
dvas
·há 3 anos·discuss
That's the thing with details; sometimes you don't know the extent or context in which they will occur.

Your perceptiveness at a particular moment could determine a good or not-so-good outcome. However, you may not have the expertise or familiarity in a domain to spot micro, mini, or normal details.

My personal takeaway is to be mindful when you are on autopilot to avoid missing details and to avoid keeping your blinders on.
dvas
·há 3 anos·discuss
I think the real world latency numbers will be interesting to see with PCIe 6.0/7.0 since adopting PAM4 modulation allows the greater bandwidth.

[0] Why Did PCIe 6.0 Adopt PAM4? There Are Many Reasons. https://blog.samtec.com/post/why-did-pcie-6-0-adopt-pam4-the...
dvas
·há 3 anos·discuss
CXL and its coherency mechanisms will be interesting to watch as the requirements for LLMs and related applications requiring large memory pools continue to grow. This includes some HPC related workloads also.

One of the use cases I have seen recently was driving down the total cost of DRAM in a larger-scale deployment of systems at AWS, Azure, Meta etc.

Pond [1] which is a memory pooling system, claims to achieve the desired performance and at the same time lowering costs as one example.

I think a look at the overall, bigger picture is important. For example considering how a system will be combined together with multiple GPU's, memory systems and other accelerators to meet the demands of applications, consider interconnects like NVLink [3] too.

For those interested, I have left a previous comment about experimenting with CXL on a local setup [0]

[0] https://news.ycombinator.com/item?id=37944691#37948761

[1] Pond: CXL-Based Memory Pooling Systems for Cloud Platforms https://arxiv.org/abs/2203.00241

[2] Intel Reveals the "What" and "Why" of CXL Interconnect, its Answer to NVLink https://www.techpowerup.com/254462/intel-reveals-the-what-an...

[3] NVLink and NVSwitch; The building blocks of advanced multi-GPU communication—within and between servers. https://www.nvidia.com/en-us/data-center/nvlink/