As toxic as Brian Krazinich was, you can’t really blame one person for the problem at Intel. Yes, he and Murthy initiated the layoffs. But then the orders were executed by mid/senior management. They are the ones who have used reviews/promos/bonuses as political weapons for as long as I ever worked there (over a decade). It was natural that the 2016 layoffs at Intel eviscerated the technical contributors while keeping the politicians, ass-kissers and powerpointers in place.
As far as I can tell Pat Gelsinger has not changed anything. The same hacks who ruined Intel are all still there, moving up the managerial ranks. Makes sense because Pat came from that culture… he practically defined it.
There’s another side to the Intel 10nm process debacle. Intel designers and architects have relied on a process and manufacturing advantage for years to overwhelm any problems they had. One of the consequences is the death of any kind of post-mortem accountability: if your product is guaranteed to make billions of dollars no matter what, why point any fingers? Management basked in the money stream. Engineers who toed the line were promoted up. Dissenters were beaten down.
This toxic environment might still be going on now if Intel maintained their process advantage… the 10nm debacle exposed the design/arch teams: their people-manager emperors had no clothes.
LOL I remember working on Cannonlake A0. The dozen (not plural) parts we got passed sort but all bricked. Turns out the PLL was randomly losing lock due to variation alone. Also the analog designers refused to run timing checks on digital control logic (if we just match the layout it would work amirite?)
I left a year after that... tbh don't see things getting any better from talking to friends. We'll see.
This will age poorly. Performance king at unconstrained power is utterly irrelevant from a financial point of view, and requires very little engineering effort to boot: shoving amps into a package until it breaks is the job of a junior engineer frankly. The rapidly dying PC/DIY market will not save Intel.
The metrics that matter financially are performance/power and performance/area, and Intel is worst-in-class in both metrics in both CPU and GPU right now.
I worked in chip design at Intel for over a decade. In the 2016 culling, I noticed they laid off a ton of smart people, but all the terrible management and fake-it-til-you-make-it engineers survived. I left very soon afterwards. I suspect the 2022 massacre will be along the same lines. Intel as an organization is not just finished, it is terminally toxic and incapable of being fixed.
LOL yeah. He lured a bunch of his old buddies from retirement with fat packages as if those old Intel-lifer hacks had any fresh ideas to contribute. Pat is literally an Intel swamp creature that somehow managed to pass himself off as some kind of tech genius despite not having been in a technical role at Intel since the 286, after which he was fast-tracked into management.
I worked in Pat's org years ago and neither he nor his lieutenants had any talent other than fighting Intel political battles.
Less cache, much smaller OOO window, AVX-512. E-core is an area play so Intel can score some multi-thread benchmarketing wins on integer heavy code that don’t have larger memory/cache footprints, don’t require much speculative depth, and naturally have high amounts of ILP. They completely fall flat on plenty of workloads. And the way Intel runs them is absurd: 10+ watts per e-core just to eek out a MT win is pure absurdity.
Until Intel has a p-core that isn’t grossly obese, they have no option but to spam e-cores just to make powerpoint slides.
Intel fanboys whine about Apple/Intel CPU comparisons, here is their answer.
The takeaway from the story: connecting a bunch of shitty chiplets together makes a shitty SoC. Except this time, Intel paid TSMC a buttload of money to make their shitty design.
LOL. Anyone who works in chip design would know much M1/M2 changed the hardware game. It is actually the dabbler enthusiast talking about how power/perf isn’t important because his LED-laden shitbox has a wall plug (muh absolute performance) that doesn’t grasp how utterly irrelevant DIY builders are in the market. Just look at the relative sales of servers, laptops and desktop and see what we care about.
Not a single second of thought is ever spent by the architects/designers on optimizing “absolute performance”. We only care about perf/area and perf/watt. It is the marketing teams that try to hype up gamer performance. Overclocking/high voltage performance requires the engineering knowledge of a freshman intern: go raise the voltage/freq, run the test program, make a SKU.
Source: worked on CPU/GPU arch/design for 20 years, including at Intel.
They know it matters, they just don’t have the competence to do it since they promoted a bunch of toadies and charlatans into their technical leadership, and also outsourced a ton of technical work to “low cost geo” so managers can brag about cutting costs.
It isn’t. TSMC has multiple customers lined up with the volume required to ramp these processes to high volume, Intel only has their own designs and whatever foundry customers willing to be an Intel guinea pig.
TSMC also has extensive experience with these machines compared to Intel.
Pat is just making shit up and hoping their stock price doesn’t crater even more.
Trusting Intel to be the torch bearer of Western semiconductor manufacturing is a grievous mistake to begin with. Intel is crippled with incompetence and corruption, government money only contributes to the dysfunction.
My org lost a few people to Intel. They all did their research and know full well the technical and managerial leadership at Intel are total clowns and that Intel is finished.
So they are going to rest and vest. They all know Intel is finished but the short term bump in pay is quite attractive for people who want to take a break.
- The Sapphire Rapids validation catastrophe proves they haven’t learned a damn thing about high quality first silicon even after all these years of getting their asses handed to them by AMD/Apple on fast cadence updates.
- Arc, enough said.
Pat Gelsinger made some big moves on his direct reports but he doesn’t have the time to perform the necessary mass purge of the mid/mid-high level management (i.e. the baby VP tier). When you run a company with 100k staff you have to delegate a lot of things, but the problem is a huge amount of the toxic management are still there, hiding in nooks and crannies and surviving.
Intel is currently throwing a lot of money around to hire people from the companies thrashing them (got a text message from a VP a couple months back), I get the feeling the Intel immune system will spit them back out upon detecting deviance from “the Intel way”.
lol this will age well. i remember designing CPUs at intel when they had like a ~2.5 gen process lead (literally 4-5 years) and the result was still barely better than competition.
what outsiders don’t realize is intel management never had to deal with competition. they spent their entire careers fighting each other in petty internecine political battles. if you think intel vs amd is a feud, you haven’t seen intel arch/design vs intel fabs. and in that kind of environment, loyalists and politicians are promoted, not people willing to critically inspect your own processes and improve things.
end result: intel has a massive competence gap. in the extremely unlikely scenario where intel can regain the process lead, they will still be behind the curve on innovation and execution.
You are completely over-complicating things. P6 derivatives stuck with “traditional” Tomasulo algorithm for way too long. Everyone else moved to pointers for arch regs long before Intel did: MIPS 10k, DEC, AMD, Intel P4, etc, it isn’t really that big of a deal and is actually a simplification from the design aspect. There hasn’t been a total overhaul of CPU arch in decades.
For whatever reason, Intel called this mechanism “marbles”. There are a bunch of names in the industry for this: PRF, arch pointers, etc… its all the same thing.
By the way, moving to arch pointers is precisely what adds additional work on retirement: you need to do a walk or checkpoint restore to revert the arch state back to where it needs to be. With P6/Tomasulo, it is free. You got it backwards.
Yeah, they are done. Worked there for 15+ years in the CPU design org. The total collapse of the technical cadre in the 2010s will be studied in business schools as a case study of how to destroy a tech company from within even as they faced no competition. Intel has a dire competence problem that is impossible to address since the vast majority of management are lifers who are only interested in preserving the only system they know and not even the CEO can take on such an entrenched bureaucracy.
Any talk of Intel beating Apple/AMD in "performance" while being behind in process technology is ignorant of the engineering metrics that really matter in the industry, as well as the actual impact of process shrinks in the year 2022.
And when it doesn’t, will you apologize for calling everyone else a fanboy because they don’t buy into your excuses?
Go compare the perf/power curves of the alder-lake cores (both P/E) versus the last-gen Apple cores from TSMC n7+. TSMC n7+ is roughly comparable to Intel 10nm ESF in transistor performance, so it is a fair comparison.
Do your research then get back to me about how the process is entirely responsible for every perf/power difference and we (the silicon design teams) are just identical robots doing the same thing across the board in every company.
I do like how you claim there is no design magic sauce, but then Apple will lose big when Intel/AMD come out with their 5nm equivalents, as in, they found some magic sauce? WTF?
LOL yeah. More powerful, i.e. it consumes more power. Fun fact: the M1 big core caps itself around the same wattage where most Intel SKU consider the core to be below stock wattage. As in, in order to achieve your “more powerful” claim, it takes Intel cores 2-7x the watts, depending on the workload, to eek out a marginal performance uplift… or sometimes just to match the M1.
Nobody in CPU design cares about unconstrained power performance. Even at Intel, they never use the PL2 power level as the design landing zone. All modeling is done at much lower power target, even below PL1.
That is to say: unconstrained power performance is not an engineering effort, it is a marketing and SKU differentiation effort. Your “more powerful” statement is a matter of how much power Intel/Apple/AMD/whoever is willing to shove into their piece of silicon, which in turn dictates the form factors and customers they can try to satisfy.
Apple only needs a few watts per big core and still get the peak perf it needs, and put that chip in all the form factors it sells. Obviously if M1 sucked down the kind of power as any Intel chip, it cannot go into an iPad, or a fanless macbook air, without totally compromising performance.
Intel on the other hand needs grossly more watts to hit that same performance, and therefore is losing badly on form factors that care about power: laptops and servers. Some form factors/customers just don’t care, which is why Intel cooks up marketing targeting the gamer market, or the 8-pound laptop market. That’s all fine, just don’t pretend Intel is not getting absolutely hammered on the CPU technical specs for the money-making markets that matter.
BTW, the DIY gamer CPU market does not matter. The 8-pound laptop market does not matter.
As far as I can tell Pat Gelsinger has not changed anything. The same hacks who ruined Intel are all still there, moving up the managerial ranks. Makes sense because Pat came from that culture… he practically defined it.