psurge·4 года назад·discussC++17 has std::hardware_destructive_interference_size which you can use in conjunction with alignas to get this behavior, see https://en.cppreference.com/w/cpp/thread/hardware_destructiv...I’m not sure whether a single target architecture can (either in theory or in practice) map to hardware with different line sizes. If so, another problem is that the compiler’s idea of the cache line size might not match the hardware’s.
psurge·4 года назад·discussAnd successfully scaling different peaks requires using different kinds of safety rope. Helpfully, the different ropes all look exactly the same.
I’m not sure whether a single target architecture can (either in theory or in practice) map to hardware with different line sizes. If so, another problem is that the compiler’s idea of the cache line size might not match the hardware’s.