Intel Unfolds Roadmaps for Future CPUs and GPUs(nextplatform.com)
nextplatform.com
Intel Unfolds Roadmaps for Future CPUs and GPUs
https://www.nextplatform.com/2018/12/16/intel-unfolds-roadmaps-for-future-cpus-and-gpus/
8 comments
Yes, but if the overall power consumption of the 14 nm part is not a significant fraction of the total package consumption, it doesn't make much sense to move it to the newer process. Also, the 14 nm factories are already churning out parts at a very predictable yield.
Disregarding the fanboyism, we all must thank AMD for the advances and much better deals we are getting these days.
2 years ago, Intel was laughing at "glued-together" CPUs, rolling their eyes at anything with more than 4 cores and more recently implying that CPUs with different process sizes was "cheating".
Look at them now..
2 years ago, Intel was laughing at "glued-together" CPUs, rolling their eyes at anything with more than 4 cores and more recently implying that CPUs with different process sizes was "cheating".
Look at them now..
> more recently implying that CPUs with different process sizes was "cheating".
Not sure where you heard that because Intel’s CPUs have different feature sizes among the layers. It’s done to cut cost.
There is a downside to “glued-together” CPUs as Zen has demonstrated - their L3 cache is splitted and connected by a relatively slow connection.
I hope Intel continues to make “non-split” CPUs where all cores have equal access to single huge L3 cache.
As for moving components off die ... IIRC the Pentium Pro has its L2 cache on a different die but in the same package and the Pentium 2 went even further with the L2 cache on a daughterboard. This isn’t new to anyone.
Not sure where you heard that because Intel’s CPUs have different feature sizes among the layers. It’s done to cut cost.
There is a downside to “glued-together” CPUs as Zen has demonstrated - their L3 cache is splitted and connected by a relatively slow connection.
I hope Intel continues to make “non-split” CPUs where all cores have equal access to single huge L3 cache.
As for moving components off die ... IIRC the Pentium Pro has its L2 cache on a different die but in the same package and the Pentium 2 went even further with the L2 cache on a daughterboard. This isn’t new to anyone.
Unisys Micro-A desktop mainframe had, IIRC, 7 chips in the same package.
It was quite remarkable.
It was quite remarkable.
Put down your AMD-branded crack pipe. Intel was talking about EMIB and moving parts of the uncore to old process nodes since 2014:
http://semimd.com/blog/2014/09/02/intel-announces-new-interc... https://www.intel.com/content/www/us/en/foundry/emib.html https://www.extremetech.com/computing/254728-intel-discusses... https://www.storagereview.com/intel_unveils_its_stratix_10_m...
http://semimd.com/blog/2014/09/02/intel-announces-new-interc... https://www.intel.com/content/www/us/en/foundry/emib.html https://www.extremetech.com/computing/254728-intel-discusses... https://www.storagereview.com/intel_unveils_its_stratix_10_m...
So this would improve performance/watt for compute but not I/O?