Qualcomm Snapdragon X Elite Performance Preview: A First Look at What's to Come(anandtech.com)
anandtech.com
Qualcomm Snapdragon X Elite Performance Preview: A First Look at What's to Come
https://www.anandtech.com/show/21112/qualcomm-snapdragon-x-elite-performance-preview-a-first-look-at-whats-to-come
67 comments
The past 5 years in personal computing has been surreal. After years of Intel dominating and stagnating the desktop and laptop market, competition from AMD (Ryzen) and subsequently Apple (Apple Silicon) has been a real treat for consumer. After years of Apple squarely beating the shit out of Qualcomm and years of Qualcomm not giving a shit due to its Android monopoly, competition from MediaTek (Dimensity) forced them to up their game. Now Apple is setting the standard for laptop performance, AMD is reviving the Windows laptop scene, Qualcomm is catching up to Apple CPU, outperforming its GPU, and realizing the Windows ARM dream. Exciting, exciting times ahead.
> and years of Qualcomm not giving a shit due to its Android monopoly
What Qualcomm has is a modem and modem patent monopoly. There were early Android SoC competitors e.g. nVidia Tegra. The issue was the modem. Not the CPU.
What Qualcomm has is a modem and modem patent monopoly. There were early Android SoC competitors e.g. nVidia Tegra. The issue was the modem. Not the CPU.
What Qualcomm did have was an undisputed patent monopoly on one of the possible ways that cellular communication could be done.
Now that 3G is being turned completely off in much of the world, the last vestiges of that advantage are going away and Qualcomm will have to learn to compete on a more level playing field.
Now that 3G is being turned completely off in much of the world, the last vestiges of that advantage are going away and Qualcomm will have to learn to compete on a more level playing field.
What alternatives are there to the current 5G Qualcomm modems?
5G is an open standard and patent holders are required to make a binding commitment to license their patents on FRAND (Fair Reasonable and Non Discriminatory) terms to all comers before their patents can become part of that standard.
Even low cost Mediatek SOCs have a built in standards compliant 5G implementation.
https://www.mediatek.com/technology/5g/5g-modem
Even low cost Mediatek SOCs have a built in standards compliant 5G implementation.
https://www.mediatek.com/technology/5g/5g-modem
Is it any good compared to what Qualcomm has to offer?
It is not bad, but people who got used to Qualcomm will complain about reception. I think most customer cant tell difference between 3 / 3.5Ghz or 8 / 12 GB Memory , but when they have a spot where they used to receive better signal they will complain. So it really depends on what you consider as good.
Which means that Qualcomm has to compete on the merits now and not just on the basis of their patent monopoly.
Qualcomm is really trying to turn things around - on all fronts.
Upstreaming is clearly a higher priority now than it's been in the past, e.g. "Upstream Linux support now available for the the Qualcomm Snapdragon 8 Gen 3 Mobile Platform" [1]
Disclaimer: I'm a Qualcomm employee.
[1] https://www.linaro.org/blog/upstream-linux-support-now-avail...
Upstreaming is clearly a higher priority now than it's been in the past, e.g. "Upstream Linux support now available for the the Qualcomm Snapdragon 8 Gen 3 Mobile Platform" [1]
Disclaimer: I'm a Qualcomm employee.
[1] https://www.linaro.org/blog/upstream-linux-support-now-avail...
This part had me the most worried. Given Qualcomm's history they really need to show they mean it otherwise they will have trough convincing people to invest in their chip. With mobile and automotive Qualcomm had a habit of dropping the support after 3 years unless the OEM paid up. As an end user i do not want to own an insecure laptop after 3 years just because the manufacturer did not want to pay qualcomm.
If they actually sustain this effort I can see this new chip becoming a success regardless if it beats the M2 or not. It only has to have decent performance and decent linux support. Fingers crossed, I hope they succeed.
If they actually sustain this effort I can see this new chip becoming a success regardless if it beats the M2 or not. It only has to have decent performance and decent linux support. Fingers crossed, I hope they succeed.
AFAIK that's just the bare minimum to get Linux booting. GPU and host of other things are missing.
That doesn't correspond to what the article itself says. GPU might not be supported yet but it doesn't look like the bare minimum either.
EDIT - looks like there's GPU support too. https://www.phoronix.com/news/Linux-6.5-MSM-Adreno-A690
~~~~~~~~
With the recent series of patches released by Linaro, the following features are enabled for the Snapdragon 8 Gen 3 Mobile Platform:
Qualcomm® Kryo™ CPUs, including DVFS (Dynamic voltage and frequency scaling) and Power Management
System foundation: Clocks, Power controllers, PMICs Low-Speed I/O: I2C, SPI, RTC, Buttons, LEDs
High-Density Storage: UFS 4.0, SDXC
High-Speed Peripherals: PCIe Gen3 and Gen4, USB Version 3.1 Gen 2, USB-C PD
Qualcomm® Hexagon™ Processor SubSystems: Audio, Sensors, Compute and Modem
Mobile Display Subsystem + DSI Engine, Touch Controller
Communication: WCN7850 Bluetooth
EDIT - looks like there's GPU support too. https://www.phoronix.com/news/Linux-6.5-MSM-Adreno-A690
~~~~~~~~
With the recent series of patches released by Linaro, the following features are enabled for the Snapdragon 8 Gen 3 Mobile Platform:
Qualcomm® Kryo™ CPUs, including DVFS (Dynamic voltage and frequency scaling) and Power Management
System foundation: Clocks, Power controllers, PMICs Low-Speed I/O: I2C, SPI, RTC, Buttons, LEDs
High-Density Storage: UFS 4.0, SDXC
High-Speed Peripherals: PCIe Gen3 and Gen4, USB Version 3.1 Gen 2, USB-C PD
Qualcomm® Hexagon™ Processor SubSystems: Audio, Sensors, Compute and Modem
Mobile Display Subsystem + DSI Engine, Touch Controller
Communication: WCN7850 Bluetooth
Question: is this the first chip created by the folks from NUVIA (the crew behind Apple Silicon), that Qualcomm acquired 2-years ago?
https://www.qualcomm.com/news/releases/2021/03/qualcomm-comp...
https://www.qualcomm.com/news/releases/2021/03/qualcomm-comp...
It's also is the design ARM (the company) is suing to be destroyed. Like literally destroyed.
I'm hoping this one and many more get stuck in legal hell for ages so we finally move away from proprietary ISAs.
ARM is proprietary
That's the point. If developing high-performance ARM cores are considered risky, maybe the vendors could switch to an ISA without these risks.
There's nothing risky about developing ARM cores. Well, other than the fact that doing it wrong is very costly. Millions of them ship every year, and there have been many third-party designs, shipped in millions of units, by many different companies, for years and years and years at this point; it was actually the primary way they (ARM) did business for a long time, until ARM realized that focusing on designing better cores than their customers was a great way to make money, as increasing design complexity put them in an overall better position to do it versus third parties. The Qualcomm/ARM dispute at its core has nothing to do with the ISA, it's fundamentally an IP dispute, concerning an existing agreement after a buyout and market pivot. These kinds of disputes aren't new.
The risky thing is "violating license agreements." Licensing a RISC-V core from a company under specific terms, getting bought out, and then changing trajectory of your product with that IP in a way that might violate the terms could result in the company coming after you. Put more simply, "violating the terms of a license agreement means you could get sued." This isn't strange. It's a complete non-story.
The other real risk is one that exists in any processor design, that it costs tens of millions of dollars to develop validated, high-end, high-performance and energy efficient processors, no matter the ISA, and tooling them is an entirely different matter. These risks mean the vast majority of Production-Ready designs come from corporations that need to ship high volume, high margin products, based on projected returns. There's relatively little actually "open" about the processors from SiFive, Ventana, Rivos, etc, other than the fact they adhere to a specific version of a ratified software standard, a PDF you can download. If you come at it from a software point of view, all of the "ingredients" are basically proprietary. You aren't getting masks, RTL files, DV tools, bringup tools, or any capability to validate any of those are what you expect. You cannot reasonably modify and reproduce them -- a single wafer on a modern process can take months to actually pattern before the packaging process even begins. And they aren't going to give it to you, because that's their competitive advantage and the reason you buy their cores, instead of their competitors cores.
The whole bellowing about "proprietary ISAs" or "ARM vs RISC-V" on places like this is mostly totally misinformed upvote farming, and has no bearing on how reality actually works.
The risky thing is "violating license agreements." Licensing a RISC-V core from a company under specific terms, getting bought out, and then changing trajectory of your product with that IP in a way that might violate the terms could result in the company coming after you. Put more simply, "violating the terms of a license agreement means you could get sued." This isn't strange. It's a complete non-story.
The other real risk is one that exists in any processor design, that it costs tens of millions of dollars to develop validated, high-end, high-performance and energy efficient processors, no matter the ISA, and tooling them is an entirely different matter. These risks mean the vast majority of Production-Ready designs come from corporations that need to ship high volume, high margin products, based on projected returns. There's relatively little actually "open" about the processors from SiFive, Ventana, Rivos, etc, other than the fact they adhere to a specific version of a ratified software standard, a PDF you can download. If you come at it from a software point of view, all of the "ingredients" are basically proprietary. You aren't getting masks, RTL files, DV tools, bringup tools, or any capability to validate any of those are what you expect. You cannot reasonably modify and reproduce them -- a single wafer on a modern process can take months to actually pattern before the packaging process even begins. And they aren't going to give it to you, because that's their competitive advantage and the reason you buy their cores, instead of their competitors cores.
The whole bellowing about "proprietary ISAs" or "ARM vs RISC-V" on places like this is mostly totally misinformed upvote farming, and has no bearing on how reality actually works.
I thought it was a licensing issue. ARM is arguing that the license that Nuvia used to develop their chip isn’t transferable to Qualcomm. Qualcomm has a license from ARM but it’s not as free as the Nuvia one, or something like that. Or have I misunderstood something?
Not gonna happen for anything big enough like a server or laptop class of computers. There is too much gap in terms of software to justify adopting a new ISA. Also, designing those high-performance ISAs cost a lot of money, both in terms of professionals involved but also resources. Any company attempting that will need to make sure there is software to run on it and that they can make money. That is beyond the reach of a lot of companies.
Yup.
Yes, the same team that got their pants sued off by like a bunch of other companies such as ARM and Apple.
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I don't care about Qualcomm and its ARM offerings for the PC - Windows side there's no reason to and Linux side because hardware longevity will be hobbled by lacking kernel and driver support beyond the first year or two.
You can't really beat Intel and AMD unless you're at least as good as supporting the hardware and peripherals and for as long. I can see Intel and AMD getting better at power use but I have a hard time seeing ARM ecosystem become as open as the PC one.
You can't really beat Intel and AMD unless you're at least as good as supporting the hardware and peripherals and for as long. I can see Intel and AMD getting better at power use but I have a hard time seeing ARM ecosystem become as open as the PC one.
> You can't really beat Intel and AMD unless you're at least as good as supporting the hardware
Worth a read:
Amazon is the most successful manufacturer of Arm server chips, accounting for just over half of Arm-based server CPUs currently deployed, while some chipmakers are also now betting on Arm-based Windows PCs.
This information comes from a report issued by Bernstein Research which estimates that nearly 10 percent of servers across the world contain Arm processors, and 40 percent of those are located in China, as we reported earlier.
But that total is beaten by just one company – Amazon – which has slightly above 50 percent of all Arm server CPUs in the world deployed in its Amazon Web Services (AWS) datacenters, said the analyst.
https://www.theregister.com/2023/08/08/amazon_arm_servers/
Worth a read:
Amazon is the most successful manufacturer of Arm server chips, accounting for just over half of Arm-based server CPUs currently deployed, while some chipmakers are also now betting on Arm-based Windows PCs.
This information comes from a report issued by Bernstein Research which estimates that nearly 10 percent of servers across the world contain Arm processors, and 40 percent of those are located in China, as we reported earlier.
But that total is beaten by just one company – Amazon – which has slightly above 50 percent of all Arm server CPUs in the world deployed in its Amazon Web Services (AWS) datacenters, said the analyst.
https://www.theregister.com/2023/08/08/amazon_arm_servers/
So? The fact that the most successful Arm server product is a proprietary one designed and used exclusively by one company literally proves OP point. It's much easier to support such deployment if you are its designer and sole user.
For desktop Linux, Qualcomm and the community are upstreaming drivers so you should be able to upgrade the kernel.
If this chip is comparable to a M2, then I would bet on Microsoft investing more in Windows 11 on ARM. There is value for them across all their product lines, from Surface devices where performance vs. efficiency is important from a battery life perspective, to Azure, where competitive products are rolling out ARM support that is really compelling from a cost perspective.
The only place that this makes sense over Intel/AMD on the Windows side is for laptops where ARM offers lower power draw, less heat, and longer battery life.
For a desktop, if you don't care about power and heat, then this will have inferior performance.
Nuvia had a core designed for server chips when Qualcomm bought them, and Qualcomm publishing benchmarks at an 80 watt TDP, tells me that their chip isn't going to be well positioned to compete on power draw, heat and battery life against next year's chips, especially without any sort of efficiency core at all.
For a desktop, if you don't care about power and heat, then this will have inferior performance.
Nuvia had a core designed for server chips when Qualcomm bought them, and Qualcomm publishing benchmarks at an 80 watt TDP, tells me that their chip isn't going to be well positioned to compete on power draw, heat and battery life against next year's chips, especially without any sort of efficiency core at all.
The Snapdragon X Elite CPU is closer to the M2 Pro / Max, while the GPU is closer to the regular M2. This makes comparisons a bit difficult without knowing price and resulting battery life.
> Showcasing reference designs for performance purposes is very typical overall for Qualcomm. This is also how the company handles their smartphone testing – in most years we’ll get to benchmark a Snapdragon mobile SoC running in a Qualcomm Reference Device (QRD) as a preview before retail devices are available. Even though they’re not a vertically integrated company, they still need to develop devices to test their own hardware, and they like to use those to initially show off their designs.
What's stopping Qualcomm from manufacturing their own phones and laptops and sell them directly to consumers?
What's stopping Qualcomm from manufacturing their own phones and laptops and sell them directly to consumers?
At least one aspect is that they don't want to compete with their largest client (samsung). And they don't have the manufacturing ability that samsung has to actually win that competition.
It would be really nice to have Raspberry Pi-like developer board with this chip. At one point Qualcomm released full documentation for their SoCs, with a publicly available manual with near complete register documentation. I think it was for the APQ8064. It even included Adreno GPU registers and some GPS/WiFi baseband related stuff.
* An unfused SoC, so no secure boot etc. The Efuse VPP pin is tied to ground so no possibility of bricking it by blowing the fuses inadvertently.
* Fully open bootloader, e.g. U-Boot based.
* Mostly complete register documentation for the SoC, that would be good enough.
* Mainline Linux support.
Such a board would take the open source world by storm.
* An unfused SoC, so no secure boot etc. The Efuse VPP pin is tied to ground so no possibility of bricking it by blowing the fuses inadvertently.
* Fully open bootloader, e.g. U-Boot based.
* Mostly complete register documentation for the SoC, that would be good enough.
* Mainline Linux support.
Such a board would take the open source world by storm.
I would look at RISC-V instead.
Competitive very high performance cores already available for licensing include SiFive P870, Ventana Veyron as well as Tenstorrent Ascalon or Alastor.
We just need the SoC.
Competitive very high performance cores already available for licensing include SiFive P870, Ventana Veyron as well as Tenstorrent Ascalon or Alastor.
We just need the SoC.
Yes but then there's the question of software support. Arm supports android which has a huge ecosystem. And there are way more linux and other obscure/niche OSes which support arm like raspbian. If there was an easy way to run arm or x86 code on risk-v like rosetta that could help, but arm still has much better support than risk v.
Box64 supports RISC-V as host ISA.
Refer to e.g. youtube to see it in action.
I have personally used qemu-user, another solution, to run ARM binaries.
Refer to e.g. youtube to see it in action.
I have personally used qemu-user, another solution, to run ARM binaries.
An X Elite board would probably be $500 though.
Impressive. I have used laptops with Snapdragon 835 and 850. Native app and battery performance are passable. I wish Microsoft and Qualcomm could bring PCs the same portable experience as Apple Silicon devices.
Looks promising. Can we get one of these in a Framework laptop now?
Judging based on how difficult it was to transition to also making AMD mainboards, I doubt we would see this for YEARS.
Doubt it, I suspect Microsoft will get an exclusivity deal going on with them so they're only sold to Windows-on-ARM machines.
From the article:
> Regardless, the primary purpose of the Linux demo was to showcase that Linux was working on the Snapdragon Elite X as well – that it’s not just for Windows – as Qualcomm has aims of getting the SoC into Linux laptops as well.
Some person on the internet [1] says "The good news is that the exclusivity of Microsoft's Qualcomm 8cx series has ended. Moving forward, we will be able to encounter the 8cx series in a greater variety of form factors. For instance, there are plans to incorporate the 8cx Gen4 into Chromebooks as well." I'm not sure if exclusivity of 8cx Gen4 is different from X Elite though.
[1] https://x.com/Tech_Reve/status/1670038184405901313?s=20
> Regardless, the primary purpose of the Linux demo was to showcase that Linux was working on the Snapdragon Elite X as well – that it’s not just for Windows – as Qualcomm has aims of getting the SoC into Linux laptops as well.
Some person on the internet [1] says "The good news is that the exclusivity of Microsoft's Qualcomm 8cx series has ended. Moving forward, we will be able to encounter the 8cx series in a greater variety of form factors. For instance, there are plans to incorporate the 8cx Gen4 into Chromebooks as well." I'm not sure if exclusivity of 8cx Gen4 is different from X Elite though.
[1] https://x.com/Tech_Reve/status/1670038184405901313?s=20
They're big on showing parallel benchmarks but nothing that would give a hint of what the actual single-core IPC is. This doesn't bode that well IMO.
Those are just the benchmarks Anandtech chose to run. Other sources ran single core benchmarks that show higher performance than any other Arm core. https://www.xda-developers.com/snapdragon-x-elite-benchmarks...
These SOCs could have a better future if they had Linux support to a satisfactory level. I wouldn't touch a Windows ARM device with a ten foot pole, unless of course I can boot Linux on it. Software support is abysmal. On the other hand, due to open source nature of Linux land, the software support is vastly superior provided that the OEM provides upstream drivers.
I wonder to what extent their 8-channel memory controller is helping. Intel has been selling 2-channel memory subsystems into the desktop and mobile market for a long time, still doing that even on 24-core CPUs. I believe the cheapest 8-channel CPU Intel offers costs $2000. Perhaps this level of competition will help them fix that.
Don't count memory channels, count the total bus width. 128 bits wide is nothing special, even if it is divided into eight channels of 16 bits. That's exactly how Intel and AMD support LPDDR, too.
So, when Apple says 128-bit or 512-bit or 1024-bit wide interface to LPDDR4x/LPDDR5, does this really mean just a number that is derived from number_of_channels x channel_width?
E.g. 128-bit memory wide bus in case of LPDDR type of memory is really just 8x 16-bit channels or, in a different word-size configuration, 4x 32-bit channels.
If that is so, my understanding is that Intel Tiger Lake with its 2x 64-bit channel design would equal to the same 128-bit memory bus width as M1, although, coupled with different type of memory chip technology - DDR4 instead of LPDDR.
E.g. 128-bit memory wide bus in case of LPDDR type of memory is really just 8x 16-bit channels or, in a different word-size configuration, 4x 32-bit channels.
If that is so, my understanding is that Intel Tiger Lake with its 2x 64-bit channel design would equal to the same 128-bit memory bus width as M1, although, coupled with different type of memory chip technology - DDR4 instead of LPDDR.
DDR4 and earlier DIMMs are 64 bits per channel. DDR5 is still 64 bits per DIMM, but split into two 32-bit sub-channels. LPDDR is typically 16 bits per channel. For processors whose memory controller supports more than one of these standards, the total bit width is what's fixed in silicon and the processor's pin count; which kind of memory the processor is connected to will determine how many (sub)channels the bus is split into.
For about two decades, mainstream consumer x86 platforms have almost always had a 128-bit memory bus. On desktop platforms with DDR4 and earlier, this can be accurately described as dual-channel, and that's the terminology marketing departments and end users are most familiar with. But it's never been accurate for mobile systems that use LPDDR, and DDR5 makes it less accurate for desktops, too.
High-end platforms like AMD's Threadripper have supported memory configurations like 256-bit ("quad channel DDR4") and 512-bit ("8 channel DDR4") and now 768-bit on the latest EPYC servers, and over the years Intel has had server or workstation platforms with 192-bit (LGA 1366 socket), 256-bit (LGA 2011), 384-bit (LGA 3467), 512-bit (LGA 4677) memory interfaces (per socket). I believe Apple was the first to ship something wider than 128-bit in a laptop, and AMD plans to be the second in a year or so (not too surprising given what they've been shipping for the console market).
For about two decades, mainstream consumer x86 platforms have almost always had a 128-bit memory bus. On desktop platforms with DDR4 and earlier, this can be accurately described as dual-channel, and that's the terminology marketing departments and end users are most familiar with. But it's never been accurate for mobile systems that use LPDDR, and DDR5 makes it less accurate for desktops, too.
High-end platforms like AMD's Threadripper have supported memory configurations like 256-bit ("quad channel DDR4") and 512-bit ("8 channel DDR4") and now 768-bit on the latest EPYC servers, and over the years Intel has had server or workstation platforms with 192-bit (LGA 1366 socket), 256-bit (LGA 2011), 384-bit (LGA 3467), 512-bit (LGA 4677) memory interfaces (per socket). I believe Apple was the first to ship something wider than 128-bit in a laptop, and AMD plans to be the second in a year or so (not too surprising given what they've been shipping for the console market).
> I believe Apple was the first to ship something wider than 128-bit in a laptop
Yes, that is now more obvious to me after your clarification and a short history walk-through. Thanks!
Given that Apple never discloses much about their design, I was never actually 100% sure if the difference would only be related to the number of memory channels and thus capability of a memory controller or there was something else that was novel and that nobody else did. I am much more familiar with the server grade CPUs and was aware, as you very neatly summarized, of the differences and high memory bandwidths available in that spectrum. I was checking just this morning how many channels there are on Epycs and last generation of Xeons!
Since we have different 128-bit wide designs available, it is interesting that Apple M1 chose to have 128B cache line size instead what others have - 64B. I never thought about that but it makes me wonder if it is more challenging to design a memory subsystem with the cache line size larger than what your DIMM actually supports.
Yes, that is now more obvious to me after your clarification and a short history walk-through. Thanks!
Given that Apple never discloses much about their design, I was never actually 100% sure if the difference would only be related to the number of memory channels and thus capability of a memory controller or there was something else that was novel and that nobody else did. I am much more familiar with the server grade CPUs and was aware, as you very neatly summarized, of the differences and high memory bandwidths available in that spectrum. I was checking just this morning how many channels there are on Epycs and last generation of Xeons!
Since we have different 128-bit wide designs available, it is interesting that Apple M1 chose to have 128B cache line size instead what others have - 64B. I never thought about that but it makes me wonder if it is more challenging to design a memory subsystem with the cache line size larger than what your DIMM actually supports.
Memory bus widths are usually measured in bits while cache line sizes are bytes. The problem isn't with having a cache line that's too big, but rather too small: DDR3 and DDR4 both used burst sizes of eight transfers of 64 bits each, for a total burst of 64 bytes. DDR5 increased the burst size to 16 transfers, and split the DIMM into two subchannels to compensate—otherwise, it would be impossible to use the full bandwidth when fetching individual 64Byte cache lines. Transferring two bursts of data from RAM (not necessarily from the same channel) to fetch a single cache line worked fine in the DDR2 era.
I see that the burst length for LPDDR4/LPDDR5 is configurable as either 16 transfers (32B) or 32 transfers (64B) which means that fetching a single 128B cache line requires Apple M memory controller to issue 2 or 4 read bursts depending on the setting used.
According to the page 78 from https://www.micron.com/-/media/client/global/documents/produ..., burst read operation will take 16 clock cycles to clock in, and roughly 4 more cycles to get the data out.
At 2133Mhz clock cycle is 468 ps or 0.46 ns so to get 64 bytes out it will take 20 cycles x 0.46 ns = 9.2 ns. This means that to populate the 128B cache line it will take at least two such bursts leading to a total latency of 18.4 ns. This latency translates to ~6GB/s of burst reads. I guess this is a number only for a single channel and it's relatively close to what Micron mentions in the PDF: "Up to 8.5 GB/s per die".
What I don't understand is how the LPDDR4 data rate transfer of 3200 MT/s (~25GB/s) is achieved then? The biggest package Micron LPDDR4 module comes in is 2 channels, hence, per their numbers we get a maximum bandwidth of 2 x 8.5GB/s = 17GB/s.
According to the page 78 from https://www.micron.com/-/media/client/global/documents/produ..., burst read operation will take 16 clock cycles to clock in, and roughly 4 more cycles to get the data out.
At 2133Mhz clock cycle is 468 ps or 0.46 ns so to get 64 bytes out it will take 20 cycles x 0.46 ns = 9.2 ns. This means that to populate the 128B cache line it will take at least two such bursts leading to a total latency of 18.4 ns. This latency translates to ~6GB/s of burst reads. I guess this is a number only for a single channel and it's relatively close to what Micron mentions in the PDF: "Up to 8.5 GB/s per die".
What I don't understand is how the LPDDR4 data rate transfer of 3200 MT/s (~25GB/s) is achieved then? The biggest package Micron LPDDR4 module comes in is 2 channels, hence, per their numbers we get a maximum bandwidth of 2 x 8.5GB/s = 17GB/s.
> The biggest package Micron LPDDR4 module comes in is 2 channels
Okay, this is wrong, I couldn't find it before but there is a larger Micron LPDDR4 module equipped with 4 channels and thus this theoretical LPDDR4 limit can be hit. E.g. MT53D1024M32D4 from https://www.micron.com/-/media/client/global/documents/produ...
Okay, this is wrong, I couldn't find it before but there is a larger Micron LPDDR4 module equipped with 4 channels and thus this theoretical LPDDR4 limit can be hit. E.g. MT53D1024M32D4 from https://www.micron.com/-/media/client/global/documents/produ...
Thanks, I often forget this distinction.
According to Wikipedia, this one uses 4nm node while M2 is on N5P.
Well, as of 13 minutes ago Apple announced the M3 which is on the N3 process.
Then when are we having Hackintoshes on ARM?
I am not sure what Qualcomm is hoping to accomplish by releasing this, rather than committing to RISC-V.
No M2 Pro comparison?
Gary Explains gave some numbers that seem to indicate its on-par or a bit better than M2 Pro at similar power levels.
https://www.youtube.com/watch?v=_8wzGkTWdP8&t=348s
https://www.youtube.com/watch?v=_8wzGkTWdP8&t=348s