Intel (Quartus FPGA compiler) | Toronto, ON, Canada
Interested in working on algorithmically-complex C++ code to squeeze out every last bit of performance? Understanding the hardware as well as the software, and building a mission-critical tool used daily by digital circuit designers? Actually using advanced computer science knowledge outside of interviews and programming competitions to optimize graph-based algorithms simultaneously for runtime, memory, and quality of the resulting solution? Then working on Quartus, Intel's compiler for FPGAs, is for you.
You will work in a downtown Toronto location, with an amazing and diverse group of talented engineers, on some of the most intellectually challenging problems in the world, and your work will directly benefit areas like AI, telecommunications, healthcare, aerospace, finance and more.
I am looking to hire specifically for the Timing Analysis team, which is responsible for both a user-visible Timing Analysis tool (used by digital designers to analyze timing problems) and the highly-optimized internal timing engine, which responds to millions of requests during a typical circuit compilation.
Hardware/FPGA knowledge is not required. Ideally, I am looking for some combination of the following: (1) ability to reason about algorithms and code optimization, (2) experience writing well-crafted C++ code as part of a large codebase, and (3) a passion for usability / caring deeply about the customer experience. My colleagues are hiring for other roles. Canadian citizens or Permanent Residents preferred.
Please feel free to ask any questions here in comments, or send a resume to evgeny dot osovetsky at my company name dot com.
I don't have a full list, but generally the Toronto office has the following types of software roles: (1) Quartus compiler - this is what takes a digital circuit netlist and tries to map it in an optimal way to the FPGA hardware - doing things like clustering, placement, routing, etc. Lots of very interesting optimization problems. Hardware knowledge is helpful but not required, it's much more important to be able to reason about algorithms and write efficient C++ code to implement them. (The team I'm hiring for is a part of this group). (2) High-level design - basically, how can we make FPGA programming accessible for software engineers who know nothing about hardware? This involves a bunch of compiler work to translate C-like languages (or even higher-level constructs, like machine learning models) automatically to a hardware circuit description, at which point the Quartus compiler from #1 above takes over. Again, hardware knowledge is optional, ability to reason about compilers / algorithms is key. (3) Device modeling - how can we model all of the enormous complexity of a real physical device (with all of its complex timing and power characteristics) into a simplified software model that the Quartus compiler can then use efficiently? Other than these 3 main groups, there are others (e.g. working on specific hardware pre-built blocks that customers can use right away, or working on combination of hardware / software / embedded firmware to make it easier to interface between FPGAs and modern memory microchips).
Intel (Quartus FPGA compiler) | Toronto, ON, Canada
Interested in working on algorithmically-complex C++ code to squeeze out every last bit of performance? Actually using advanced computer science knowledge outside of interviews and programming competitions? Optimizing graph-based algorithms simultaneously for runtime, memory, and quality of the resulting solution? Understanding the hardware as well as the software? Then working on Quartus, Intel's compiler for FPGAs, is for you.
You will work in a downtown Toronto location, with an amazing and diverse group of talented engineers, on some of the most intellectually challenging problems in the world, and your work will directly benefit areas like AI, telecommunications, healthcare, aerospace, finance and more.
I am looking to hire specifically for the Timing Analysis team, which is responsible for one of the most critical components in the Quartus compilation flow (all compilation decisions are ultimately aimed at making the resulting FPGA design faster, and to determine the impact of various decisions on speed you need a robust and efficient timing engine). My colleagues are hiring for other roles. Canadian citizens or Permanent Residents preferred.
Please feel free to ask any questions here in comments, or send a resume to evgeny dot osovetsky at my company name dot com.
As far as I know, visa support is only provided in exceptional circumstances (e.g. PhD in an area directly related to FPGAs / exact fit for a specific, hard-to-fill open position). This is for the Toronto office, our other offices may have different policies.
I don't have any specific numbers to share (and in any case it depends on the grade level you're hired at), but it's definitely competitive (including excellent benefits - some of which are quite unique, e.g. covering some of the costs of part-time graduate studies for those who choose to pursue them).
Ability to reason about and optimize algorithms and data structures (graphs, trees, etc) is key. C++ knowledge/experience strongly preferred. Other than that, it would be good to have some understanding of hardware / computer engineering concepts, but it's not required - that can be learned on the job. We're hiring at different experience levels, from fresh undergrads to experts - for my specific position I would prefer someone who has done at least a couple of years of similar work, but as I mentioned there are several groups hiring.
Part-time - not really, but if you're available for a full-time 12 to 16 months internship (and have the legal right to work in Canada) please get in touch.
Intel (Quartus FPGA compiler) | Toronto, ON, Canada
Interested in working on algorithmically-complex C++ code to squeeze out every last bit of performance? Actually using advanced computer science knowledge outside of interviews and programming competitions? Optimizing graph-based algorithms simultaneously for runtime, memory, and quality of the resulting solution? Understanding the hardware as well as the software? Then working on Quartus, Intel's compiler for FPGAs, is for you.
You will work in a downtown Toronto location, with an amazing and diverse group of talented engineers, on some of the most intellectually challenging problems in the world, and your work will directly benefit areas like AI, telecommunications, healthcare, aerospace, finance and more.
I am looking to hire specifically for the Timing Analysis team, which is responsible for one of the most critical components in the Quartus compilation flow (all compilation decisions are ultimately aimed at making the resulting FPGA design faster, and to determine the impact of various decisions on speed you need a robust and efficient timing engine). My colleagues are hiring for other roles. Canadian citizens or Permanent Residents preferred.
Please feel free to ask any questions here in comments, or send a resume to evgeny dot osovetsky at my company name dot com.
Intel (Quartus FPGA compiler) | Toronto, ON, Canada
Interested in working on algorithmically-complex C++ code to squeeze out every last bit of performance? Actually using advanced computer science knowledge outside of interviews and programming competitions? Optimizing graph-based algorithms simultaneously for runtime, memory, and quality of the resulting solution? Understanding the hardware as well as the software? Then working on Quartus, Intel's compiler for FPGAs, is for you.
You will work in a downtown Toronto location, with an amazing and diverse group of talented engineers, on some of the most intellectually challenging problems in the world, and your work will directly benefit areas like AI, telecommunications, healthcare, aerospace, finance and more.
I am looking to hire specifically for the Timing Analysis team, which is responsible for one of the most critical components in the Quartus compilation flow (all compilation decisions are ultimately aimed at making the resulting FPGA design faster, and to determine the impact of various decisions on speed you need a robust and efficient timing engine). My colleagues are hiring for other roles.
Canadian citizens or Permanent Residents preferred.
Please feel free to ask any questions here in comments, or send a resume to evgeny dot osovetsky at my company name dot com.
Interested in working on algorithmically-complex C++ code to squeeze out every last bit of performance? Understanding the hardware as well as the software, and building a mission-critical tool used daily by digital circuit designers? Actually using advanced computer science knowledge outside of interviews and programming competitions to optimize graph-based algorithms simultaneously for runtime, memory, and quality of the resulting solution? Then working on Quartus, Intel's compiler for FPGAs, is for you.
You will work in a downtown Toronto location, with an amazing and diverse group of talented engineers, on some of the most intellectually challenging problems in the world, and your work will directly benefit areas like AI, telecommunications, healthcare, aerospace, finance and more.
I am looking to hire specifically for the Timing Analysis team, which is responsible for both a user-visible Timing Analysis tool (used by digital designers to analyze timing problems) and the highly-optimized internal timing engine, which responds to millions of requests during a typical circuit compilation.
Hardware/FPGA knowledge is not required. Ideally, I am looking for some combination of the following: (1) ability to reason about algorithms and code optimization, (2) experience writing well-crafted C++ code as part of a large codebase, and (3) a passion for usability / caring deeply about the customer experience. My colleagues are hiring for other roles. Canadian citizens or Permanent Residents preferred.
Please feel free to ask any questions here in comments, or send a resume to evgeny dot osovetsky at my company name dot com.