The apparent driver here isn’t about AMD wanting to get into the FPGA business. The real motivation appears to be a combination of platforms and programmable chiplets. There are two problems that programmable chips address https://semiengineering.com/amd-wants-an-fpga-company-too/
-SMIC is shipping 14nm finFETs, with a 7nm-like process in R&D.
-Yangtze Memory Technologies (YMTC) recently entered the 3D NAND market with a 64-layer device. A 128-layer technology is in R&D.
-ChangXin Memory Technology (CXMT) is shipping its first product, a 19nm DRAM line.
-China is expanding into compound semis, including gallium nitride (GaN) and silicon carbide (SiC).
-China’s OSATs are developing more advanced packages.
An expanding attack surface in hardware, coupled with increasing complexity inside and outside of chips, is making it far more difficult to secure systems against a variety of new and existing types of attacks https://semiengineering.com/hardware-attack-surface-widening.... Per Paul Kocher “AI will help attackers in a number of ways, where behaviors that used to be unique to humans can now be automated in ways that are lot harder to distinguish from humans"
Hi there, I'm seeing more and more remote roles that our posted on our semiconductor publication site for engineers due to the talent shortage. If you dig into some of the roles, it indicates flexible locations.
https://semiengineering.com/jobs/ . Best of luck
Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows of the processor and SoC https://semiengineering.com/will-open-source-processors-caus...
https://semiengineering.com/5nm-vs-3nm/ TSMC’s 5nm technology is 15% faster with 30% lower power than 7nm. A second version of 5nm, due out next year, is 7% faster. Both versions also will use EUV.
Scaling will continue in conjunction with packaging, but whether that’s Moore’s Law is debatable. The economics of traditional shrinking are gone. It now costs more per transistor at each new node. And the power/performance improvements have sharply diminished from pure scaling, probably into the range of 10% to 15% versus 30% to 50%. However, by combining architectural improvements (neural nets, moving memory closer to processors and vice versa, faster interconnects) and by stacking memory on die or embedded them in the same package, it’s possible to achieve orders of magnitude improvements in performance and power. This has been called More than Moore, and TSMC is now calling it More Moore.
Clean data is essential to good results in AI and machine learning, but data can become biased and less accurate at multiple stages in its lifetime—from moment it is generated all the way through to when it is processed—and it can happen in ways that are not always obvious and often difficult to discern https://semiengineering.com/where-data-gets-biased/
Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency https://semiengineering.com/chiplets-faster-interconnects-an...
Scaling certainly isn’t dead. There will still will be chips developed at 5nm and 3nm, primarily because you need to put more and different types of processors/accelerators and memories on a die. But this isn’t just about scaling of logic and memory for power, performance and area reasons, as defined by Moore’s Law. The big problem now is that some of the new AI/ML chips are larger than reticle size, which means you have to stitch multiple die together. Shrinking allows you to put all of this on a single die. These are basically massively parallel architectures on a chip. Scaling provides the means to make this happen, but by itself it is a small part of total the power/performance improvement. At 3nm, you’d be lucky to get 20% P/P improvements, and even that will require new materials like cobalt and a new transistor structure like gate-all-around FETs. A lot of these new chips are promising for orders of magnitude improvement—100 to 1,000X, and you can’t achieve that with scaling alone. That requires other chips, like HBM memory, with a high speed interconnect like an interposer or a bridge, as well as more efficient/sparser algorithms. So scaling is still important, but not for the same reasons it used to be.