There are many reasons.
The main one is that no architecture exists that models such a complex ternary processor.
At most, there are "on paper" implementations of much less complex architectures; no one has addressed the problem at this level.
Having a complete architecture and its hardware implementation now allows us to start developing software on something other than an emulator.
> ----
I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary?
> -----
No, it's a processor that's available now, both the current hardware implementation (on FPGA) and the Verilog/VHDL description for implementation on other architectures (ASIC?), as well as the specifications made available under license.
>----
Is there a compiler?
>----
Hmm, but I mentioned it in the paper; currently, a working cross-assembler (obviously) and a high-level language based on Rust are being designed/built.
>----
How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA?
>----
This is an interesting question; the answer is: currently, no.
We intend to provide (soon) comparative tests of this type.
I'm the author. The 5500FP is a complete 24-trit balanced ternary RISC
processor implemented on an Efinix Trion T20F256 FPGA, with a custom
open hardware development board (GargantuRAM).
The ISA is fully documented, including instruction formats, privilege
model, and a trit-based data hierarchy.
Oh, I don't think at all that this method of operation (Tomasulo?) is remotely close to a real dataflow in terms of efficiency and complexity. But as I wrote, dataflow is another story ;)
ok, now i can say for sure, you didn't read the site well at all. you didn't even read my answers well. maybe you would have understood that now mosfet level design is already happening but it only concerns the CPU (if you want to deal with the mainboard, fine, you will have read that it is open hardware). I don't understand what you need such low level technical details for, it is obvious that i am not here to share them. If you want to make a CPU do it too, in the end we will see who did it better. now excuse me I have some serious work to do.
Thanks!
Ternary data is definitely more efficient than binary, regardless of your use, not just for AI. I honestly don't know if it's faster, can you give me information on where you read that?
I imagine it's possible even if quite difficult to merge the two architectures, but maybe it's really easier to start everything from scratch as far as hardware is concerned.
What do you mean by ternary addressing? The address bus is also in ternary so even in this case fewer wires and more addresses available!
Ok, maybe that's not clear, probably my not-so-perfect English is a problem.
The dataflow architecture was the initial idea. What I'm talking about now is the ternary processor, a normal VonNeumann processor with ternary data and ternary arithmetic.
This may eventually form the basis for the dataflow processor, but right now I'm talking about and building the ternary processor (Of course dataflow architectures are quite different and unconventional, but that's in the future, I'm not talking about it now).
As for address management, as I said the mainboard does it all, but I didn't care to go that low in detail, it's all a simple VHDL function in an FPGA.
It already comes to the FPGA in "ternary encoded bunary" from external circuits.
Yes, the serial buffer is included in the motherboard. The problem is not so much for OUT but for IN, if the buffer fills up.
As for the bus addresses, the counter program starts from the lowest address. The mainboard obviously knows how much RAM is present and performs a translation to the first available low address. Nothing transcendental.
I did not understand the connection with VonNeumann architectures, this is a classic vonneumann architecture, only that the information is in base 3...
Anyway you seem to be really very expert, certainly more than me (I am mainly a programmer and I had to learn these things at low level practically by myself), you could actively help the project...
Uhmm..actually the OUT instruction ends immediately after its normal cycle. the character is sent to the mainboard that reads it and puts it in a buffer and passes from a buffer. (it's more complex, if you want we can discuss)
The external BUS is 24 trit. the motherboard converts it by encoding it into binary and the data is stored on 48bit RAM. We don't have native ternary RAM yet unfortunately, but it was the only way to have some memory and use the processor.
I don't quite understand what idea I describe in the OP you're referring to.
And I don't understand what ternary operations might be useful for neural networks (we've had contact with Korean researchers asking about this processor for neural networks).
The specifications obviously exist, but I don't think it's a good idea to put them here on a generic site! I think the marketing phase will take a while longer and as you may have read on the site, we're still fixing things here and there and we need a marketing apparatus.
Thanks!
We sold about 30 CPUs of the old version, then we had to stop because the main component was not available for years, right after the pandemic. Now we use an alternative component that is also less expensive and we have added several new features.
The current development board is not fully functional, we are working on ETH, RTC and also fixing a few other things. We expect it to be fully functional and available by April 2025.
The OS is actually just very simple; it boots an image from SD, sets up the interrupt table, initializes a list of free memory and that's it for now. This part will be OpenSource so that we can take inspiration to make something better. The development board (mainboard) will also be open hardware and should be listed on GitHub. The macro assembler is freeware, but only because (currently) the code is really a bit messy!
Thanks!
Of course it can't be binary, but it reads purely ternary electrical signals.
You can see an example of the assembly in one of the figures on the web page (even if it's an old listing).
Expect all the normal operations a binary computer/processor does (load, store, jumps, subroutines, etc.) with the addition of ternary logic functions.
It's clear that the whole thing is encoded in balanced ternary :)
We do not currently have any integrated circuits, all the circuits (and PCBs) are entirely designed by me.
What I said is that we are using a manufacturing process to do the VLSI layout to integrate everything into a single component, but currently it is not.
That code in the figure is an old code, honestly it's an old screenshot that I don't even remember what it corresponds to, but your analysis is basically correct, even though I used absolute addresses before while now everything is relative to the current address.
I'll try to answer a bit of everything:
- yes, R0 is constantly set to 0.
- ANYI is a ternary function (ANY) that uses an immediate (ANYI). It does nothing but load the immediate value into the register indicated as the first operand.
- Yes, it is a balanced ternary, and clearly negative addresses are correctly interpreted
>out 50(r0) r2 ;output on console0?
out 60(r0) r2 ;output on console1?
- Exactly. 50 and 60 are the addresses of the two serial ports on the motherboard.
- R26 is the return register set by JSR
-Addressing is at tryte level and an instruction is always 4 trytes long. You are right that it seems a bit strange, but it is a compromise that I had to accept and that I think was the best solution to implement. (I am happy to note that your doubt was also our strong doubt during the design phase, it means that we are considering the same problems...)
-There are the dimensions of the data to operate on as a suffix of the instructions (like on motorola 68000) for which there is an LD.T (load tryte), LD.S (load short) and LD.W (load a whole word of 24 tries).
There are also instructions that load/save by addressing the memory as if it were a stack for example PUSH.W (R20),R4
>Even again each instruction is 4 tries, so we could eliminate the low bits and >move... oh, I forgot that it is ternary, it does not matter.
You think I didn't think about it? ;)
- The IO space is separate, in the end it cost me almost nothing and I did it.
The RISC features that I have kept are essentially 2:
- Constant instruction length
- Memory access only with Load/Store
In fact among the RISC things that I could remove in a future version are precisely the single access to memory only with LD/ST, it is true that it is a main feature of RISC, but it is also true that it could be a problem for code density. But it is something that I will see on the 48-trit architecture
>This may sound harsh, but to me the architecture looks both fairly conventional, and at the same time like a bit of a mess, which would be fine for a hobby project, but not for something with a website making grandiose claims and clearly intending to be a commercial product.
-That it is "conventional" ok, (even if none of the conventional architectures are ternary, but whatever...) that it is messy, what do you mean?
The website says what the project actually is. I'm glad they are grandiose things, but that's it.
And yes, we want to become a commercial product soon.
If you have suggestions or other specific questions, I'm here to answer you ;)
There are many reasons. The main one is that no architecture exists that models such a complex ternary processor. At most, there are "on paper" implementations of much less complex architectures; no one has addressed the problem at this level. Having a complete architecture and its hardware implementation now allows us to start developing software on something other than an emulator.
> ---- I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary? > -----
No, it's a processor that's available now, both the current hardware implementation (on FPGA) and the Verilog/VHDL description for implementation on other architectures (ASIC?), as well as the specifications made available under license.
>---- Is there a compiler? >----
Hmm, but I mentioned it in the paper; currently, a working cross-assembler (obviously) and a high-level language based on Rust are being designed/built.
>---- How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA? >----
This is an interesting question; the answer is: currently, no. We intend to provide (soon) comparative tests of this type.