My guess that it's happening mostly due cache conflicts. With 1024 for a simplified L1 with 32kb you can fit exactly 8 lines of the inner dimmension in the cache, which means that (0,8,0) would have the same cache location as (0, 0, 0), which is bad for tiling
Was it a university like ETH Zürich, where anyone can get in but there is a limited number of spots from the second year onwards? Then it really made sense to suggest that