I'm 60 in a few days. I slid into Verilog (now SystemVerilog) about 12 years ago, mostly on FPGAs. These days I've got more work than I know what to do with. I'm planning on retiring in December.
There's something to be said for a less common role, even if it does give me a splitting headache every now and then.
My late father-in-law was a manager at Hughes working on Surveyor 1. My wife shared his (unpublished) notes and audio recordings of the the project with me. It was an absolutely remarkable achievement. I can confirm that the Hughes team was devastated that Luna 9 got there first, however they actually learned quite a bit from the Luna 9 video feed.
It should also be noted that Luna 9 was a relatively hard landing, not suitable for a crewed spacecraft. Surveyor 1 was the first soft landing, and a prototype for the missions that would follow.
All inputs have MUTE ALT 3-4 selected.
ALT 3-4 is selected for Control Room Source.
Assign to Main Mix is selected.
Ctl Room/Submix level is at the Unity detent.
Main Out L/R send the final mix to the amplifier inputs.
Headphones in Phones.
This keeps the headphones working independent of the Main Mix level setting.
Did I have to stare at page 26 of the manual for about an hour to figure this out? Well, yes. :-(
An ancient 8 channel Mackie sound mixer to the left and slightly north of my keyboard. Other than inputs from the main computer, it pulls in audio from a bunch of other stuff/computers in the room, has a handy 1/4" headphone jack with volume control, and lets me instantly mute/mix any way I want without fiddling with keyboards or mice.
Output is to the CD inputs on a Sony mini audio system I bought on my way through Singapore in 1989.
For the hardware I was using, the downstream CDR was actually doing a reasonable job locking on the spread-spectrum clock, such that PCIe negotiations would sometimes work through quite a few states without error (I was watching the state machine in Xilinx/Vivado's ChipScope), before inevitably failing when the CDR lost lock.
From the comments: "Protip: don’t try to be fancy and provide a local REFCLK from an independent oscillator. Always use the host’s REFCLK as it may be spread spectrum modulated for EMI compliance in most PC systems."
Someone handed me a non-functional prototype system a few years ago (the first time I'd encountered PCIe), and it had a local REFCLK and an upstream Android-style host which, indeed, had enabled spread-spectrum clocking. Took me two miserable weeks to figure that one out.
Oddly enough, I never met any of the coders. The entire code base turned up on mag tapes from Belmont, CA. I was working in Toronto. I was very much a newbie, so I didn't form an educated opinion on code quality. There were very few bugs, I do remember that.
There was a lot of code, about 1.5 million lines over two version of Oracle, which included a bunch of applications as well as the RDMS.
I can't speak to security, but I bought a Mi Mix 2S some time ago and put LineageOS on it. Definitely check that the frequency bands the phone supports are utilized by your carrier.
(The fastboot screen on that phone has a wee little bear wearing a People's Liberation Army hat. Take from that what you will.)
Track down a syntax-aware code search/database tool (if your IDE doesn't have one). For me it was/is GNU ID Utils. At some point you'll be handed thousands or millions of lines of someone else's code, and you will need to find things quickly and completely.
Also, turn on all compiler warning flags all the time. Some compiler warnings aren't triggered unless optimization is enabled, so turn that on every now and then during development and see if any warnings pop. If you're handed thousands of lines of someone else's code and it's riddled with warnings, fix them first.