The complementary codebase presented in the research paper is rv32emu, an efficient RISC-V instruction set simulator, available under the MIT License. See https://github.com/sysprog21/rv32emu
I am a faculty member at a university, and the main reason I initiated this project was to create a practical learning environment for my students. I have noticed that many tools labeled as 'C compilers' only partially implement the C language, which has been a source of frustration for me. My goal is to demonstrate how to build a basic C compiler and enhance it to include some key features of the C99 standard, as well as optimization strategies commonly found in contemporary optimizing compilers. Despite its modest size, this project is robust and capable of self-hosting, meaning that students have the opportunity to develop an optimizing compiler that can compile its own code, progressively refining it for improved instruction per cycle (IPC) and better code density. Unable to find an existing one that met these expectations, I wrote a new one with my students.
While initializing shecc, it automatically creates a visualized control-flow graph and dominator tree. These can be visualized using Graphviz. To view them, execute the command "make check-snapshots" and then inspect the created CFG.dot and DOM.dot files.
Yes, consider the case of shecc. It requires just a handful of C code lines to interpret directives set in the C preprocessor. Unlike relying on existing tools like cpp, as, or ld, shecc stands alone as a minimalist cross-compiler. This design could be particularly beneficial for students delving into the study of compiler construction. See https://github.com/sysprog21/shecc/blob/master/src/lexer.c#L...
Shecc is a self-compiling compiler for 32-bit Arm and RISC-V architectures, focusing on a subset of the C language and incorporating basic optimization techniques. It generates executable Linux ELF binaries for ARMv7-A and RV32IM and includes a minimal C standard library for GNU/Linux I/O. Written in ANSI C, it is broadly compatible and features an integrated machine code generator, removing the need for external tools. The compiler uses a two-pass process for syntax checking and translating operations into machine code, and has a register allocation system for RISC-style architectures. Additionally, it includes an architecture-independent, SSA-based middle-end for enhanced optimizations.
Since version 1.6.0, regarding SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, and AES extension, SSE2NEON have achieved 100% coverage, meaning that it can translate the existing code with Intel intrinsics into the Arm/Arm64 counterpart.