Serious question: does Figure 1 in the article make sense to anyone? If you understand the symbols, do you look at the diagram and it's clear how logistics works?
The short answer is the "14-day" rule, which doesn't allow development of the embryo beyond 14 days. The article gives specifics under the heading "Ethical and legal compliance"
It's unlikely that you'd get a simultaneous tie; you'd expect one computer to go bad before the other. But I think in that case, the astronauts switch to the Backup Flight System, the fifth computer.
Mission STS-9 had two computer failures, causing landing to be delayed by 7 3/4 hours. They carried a sixth computer as a backup for following missions.
As far as how the voting works, each computer has a signal indicating what it thinks the status is of each computer, including itself. (Computers can detect many failures from self-checking, such as parity errors.) Each IOP uses these votes to determine the "redundant set", calculating the votes in hardware. The status is also displayed to the astronauts in a 5×5 grid. Astronauts can power down a computer or reboot it.
There have been a fair number of GPC failures [1], and computers have been voted out. I haven't looked closely enough to see how many were "disagreements" versus hard failures or self-check failures.
I don't know if these boards were flown. They were coated with conformal coating (which I hate for reverse-engineering), which is usually omitted from prototypes. I believe that bodge wires are okay for flight if they are done properly.
Yes, the low density and TTL chips (instead of MOS) helped against radiation. When the Shuttle computers moved to semiconductor RAM, they needed extensive error correction, as well as a process that constantly fixed bit errors, as the memory would get multiple errors per flight due to cosmic rays.
As far as redundancy, it's complicated. During critical flight phases, four computers would run the main software (PASS, Primary Avionics Software System), while the fifth computer was ready with the Backup Flight Software (BFS). The backup software was written by a completely different team to ensure that a software bug couldn't crash all the computers at once. In orbit, they used fewer redundant computers to free up computers for payload operations and stuff.
The four computers constantly checked the results from each other and would vote out a faulty system. Voting ensured that a bad computer couldn't vote out the good ones (Byzantine failure). Moreover, the actuators hydraulically voted on the results from the computers: if one computer tried to push a valve in a different direction, the three good computers would physically overpower the bad computer's action at the level of the hydraulic pistons.
CAD was a very incremental process. Early chips were drawn by hand and the Rubylith masks were cut by hand with the help of a Coordinatograph. Later, Intel used a Xynetics plotter to cut the Rubylith. By 1974, layouts were digitized with a Calma GDS I so repeated cells could be handled automatically. By the time of the 8087, there was a lot of automation.
You might think that the 8087's shifter would be a regular grid, easy to lay out by hand. It turns out to be very optimized and irregular. (I traced it out by hand and it was a pain.)
Yes, you can use a "logarithmic shifter". The CDC 6600 supercomputer (1964) used that approach. The tradeoff is that you need more stages with the logarithmic approach (six versus two for 64 bits).
If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifters. I don't know how the circuit area compares between the two approaches--two more complex stages vs six simpler stages--but I suspect the two-stage approach wins.
That's a very interesting board! It came out in 1976 (four years before the 8087) and cost $499 assembled, equivalent to $2900 in current dollars, so it was expensive. It was really a decimal processor built from simple TTL parts, and had four microcoded instructions: add, subtract, multiply, and divide. Arithmetic used the 74LS181, the very popular ALU chip. (It did multiplication with repeated addition; there's no ROM with digit products, unless that was a later version.) The "small RAM" was very small by modern standards: four 4-bit registers that each held 16 digits. Each register was implemented with a 74S189 chip.
The microcode is available, so it would be a fun project to write a simulator that runs the microcode.
On a complete tangent: there's a drawing of an iceberg halfway through the article, the typical vertical shape with 10% above the surface. It turns out that icebergs don't float that way; they rotate until they are mostly horizontal. It's one of those things that once I found out, I see wrong icebergs everywhere.
I don't think you can count PDP-10 things (Internet, BASIC, 8080 emulator) to support the influence of the PDP-11, since they were completely different computers. The PDP-10 was a 36-bit mainframe, while the PDP-11 was a 16-bit minicomputer.
I'd suggest the Datapoint 2200 as the most influential minicomputer of all time since half of you are using an instruction set based on it and it is largely responsible for the creation of the microprocessor.
Now mostly forgotten, the Datapoint 2200 was a programmable desktop computer introduced in 1970. It had a processor built from TTL chips, along with shift-register memory from Intel. Datapoint discussed with Intel and Texas Instruments the possibility of building a single-chip processor to replace the board of TTL chips. TI was first with the TMX 1795 processor, followed by Intel's 8008, both copying the Datapoint 2200 instruction set.
Datapoint decided that these chips didn't have enough performance and fatefully gave up rights to them. TI tried to sell the TMX 1795 to Ford, but got nowhere and abandoned the chip. Intel decided to sell the 8008 as a standalong microprocessor, which was used in early personal computers like the Mark-8. Intel improved the 8008 to form the 8080, then made a somewhat compatible 16-bit version, the 8086, which started the x86 architecture. (Because the Datapoint 2200 was little-endian (to use shift-register memory), x86 is little-endian.)
To summarize its influence, without the Datapoint 2200, the microcomputer industry would have been greatly delayed (since the 4004 wasn't suitable for a personal computer) and x86 wouldn't exist.
The 8087 has one metal layer, which makes power distribution more challenging. You want to keep power distribution in the metal, so for the most part the pattern is two interdigitated trees for power and ground. There are a few places where the lines need to cross, which is accomplished with a short polysilicon connection underneath. The two clock lines are also kept in metal whenever possible.
The die photo at the start of the article shows some of the power distribution (the thick white lines around the edge and through the die). I have a close-up shot of the adder's metal layer in the article, showing the thick power and ground metal lines that run next to the adder.
As far as capacitors, there are some capacitors for specific things, but no decoupling capacitors. I think the capacitors are mostly to tweak the timing, if a signal needs to be delayed slightly.