This is a bit confusing, as one of the special/unique properties of Graphene is that it doesn't have a bandgap.
If we're talking about core semiconductor applications, other 2D materials which have much larger bandgaps than the 0.6 eV reported in the paper, are much more favorable (specifically from TMD sub family, MoS2 for NMOS and WS2/WSe2 for PMOS).
To continue the patterning roadmap, many techniques were considered back in the day, including 157 litho v. NIL v. EUV v. Direct Self Assembly. For NIL, the biggest issue was defect density...why NIL found a niche in disk drive applications (Toshiba early champion) where you have a lot of redundancy built in
Because of EUV's insane cost / complexity, many older litho techniques (NIL, Direct Self Assembly) are making a comeback...NIL is a great option for lower cost patterning applications, like optical/photonic components (Magic Leap etc)
TSMC shares deep history with ASML via Philips (Philips was the first investor in TSMC, and ASML was started off as a Philips spin off).
Most of today's advanced litho (EUV) was actually funded/developed in American labs (Berkeley lab etc). The US was ahead in litho for awhile...but GCA folded and ASML acquired Cymer (based in San Diego, develops light sources for EUV) and SVG.
TSMC has a couple of advantages: 1) Focus exclusively on manufacturing, not design, 2) Large volume customers/products (Apple, AMD, NVIDIA etc), but especially Apple/iPhone. The process technology /manufacturing is tightly coupled to design specs. This provides a faster manufacturing learning curve.
-Intel screwed up by missing mobile / pushing out EUV adoption. Since they also design their own chips, they compete with any potential foundry customers in several markets (ex: data center), which is why they haven't been able to grow their foundry services division that much. TSMC is friendly with everyone and does one thing: manufacture chips in the fab.
Intel is attempting to catch up now by placing several orders for the next version of EUV, High NA EUV. They've also stated that with their planned process innovations ("RibbonFET" and "PowerVIA"), they will have a better process than TSMC at the 18A node (1.8 nm).
-For Samsung, their core business is more memory/displays. Memory lags logic in process technology innovation.
On the logic side, Samsung has made the leap to Gate-all-around transistors (next evolution of transistor, succeeding FinFET) before Intel/TSMC but seems to be facing yield problems.
TSMC is the top dog now, but things are going to get interesting as we go <3, 2 nm...
2.5D is connecting chips laterally on an interposer. Full 3D IC wafer level Packaging would be stacking wafers on top of each other a in dense, heterogenous, 3D configuration - i.e. "memory near compute"
Their CNT patent portfolio is being licensed by a company called Black Diamond Structures, which is a joint venture with SABIC. They’re looking at battery applications.
In theory, you achieve high power and long charge-discharge lifetimes with graphene-based supercapacitors
The Graphene Flagship is focused on developing methods for combining few-layer graphene and silicon nanoparticles to obtain high performance silicon-graphene anodes.
These new methods need to be cost- effective, scalable and compatible with commercial battery electrode fabrication methods (current bottlenecks). Progress continues to be made in scaling up capacity and size. Flexible graphene supercapacitors were on display at the recent Mobile World Congress
Major Conferences - Graphene Week, Mobile World Congress (Barcelona + SF), National Graphene Association (inaugural conference was Oct 2017)
Major universities in the US - UT Austin, UPenn, MIT, Stanford, Rice, Berkeley. Lot of activity in Korea, Japan, and China
Companies - Various companies on growth side. Lot of companies doing work in composites and coatings. Various startups looking into supercap, audio, sensor, battery, and water filtration applications
Vs. Carbon Fiber, it depends on the application and intended use case
Re: aerospace, from a recent report, "Graphene can give multifunctional benefits to composites, including increased mechanical properties and conductivity. To protect against lightning strikes, the composite structures of aircraft contain metal meshes or have embedded conduc- tive wires. Graphene-containing composites could provide lightning-strike protection with the advantage of a simplified production process and weight reduction.
This year, a team comprising engineers and scientists from Airbus, Aernnova and Grupo Antolin have developed a prototype aircraft component using a graphene- based composite material. A section of the horizontal tail plane leading edge (HTPLE) of the Airbus A350 XWB was manufactured using industry standard resin transfer moulding of a graphene-based composite. The performance of this prototype compo- nent will be validated through electrical, mechanical and impact testing during the Core 2 phase."
Many applications of Graphene are already on the market (ex. lighter and stiffer bicycle frames, bicycle tires, sports equipment, electronic inks and paints etc). However, these are based on lower quality Graphene powders or nanoplatelets (essentially a commodity at this point) which are used as an additive to a starting epoxy or resin material.
Chemical Vapor Deposition (CVD) is the method used to produce the highest quality graphene (usually on Copper). Several companies (Graphenea etc) have scaled up CVD and continue to work towards much lower $ / m^2 targets in the near future.
The main challenge in the industry is currently the transfer step. Current methods to transfer Graphene from growth substrate to target substrate are inefficient and not amenable to high volume manufacturing.
"Roll to Roll" (what the paper is referring to) aims to solve this - companies like Samsung, LG, and Sony have been exploring Roll to Roll systems for flexible electronics/display applications.
After flexible applications, the next step is to enable CMOS compatibility / transfer to Silicon wafers. I'm the co-founder of a company in Austin that is working towards this.
If we're talking about core semiconductor applications, other 2D materials which have much larger bandgaps than the 0.6 eV reported in the paper, are much more favorable (specifically from TMD sub family, MoS2 for NMOS and WS2/WSe2 for PMOS).
This has been needlessly hyped, like this video...https://www.youtube.com/watch?v=gWUX2OTqkEo&ab_channel=Georg...
Graphene is better off for twisted bilayer superconductors, but this is much further down the road: https://crommie.berkeley.edu/research/tlbg/