When I first discovered OPAMPs I my teen years while self learning the electronics I was astonished by the beauty and power of an abstract opamp: the mythical component with infinite differential voltage gain, zero common mode gain, infinite input impedance and zero output resistance.
This marvelous device can only exist, without destroying the world by its infinite output power, by staying in equilibrium defined by negative feedback. /s
You have to appreciate the reason it was invented in Bell Labs: analog computers, which primary applications at that time were in military applications for computing artillery solutions.
Now, as a professional EE, I still think fondly of them, even though I know well about their real life limitations.
My advice is to try to stay first at ideal OPAMP abstraction level to appreciate the mathematical usefulness of that abstract construct.
This is almost entirely how professionals use them.
I can only lament the educational system, which invariably makes the students miss the forrest for the trees by not presenting well the power of ideal opamp
Emergency Brake Assist would help if the van was equipped with it.
Swerving at the last moment and without warning would not be possible because EBA would activate brakes earlier and you would be able to see van's stop lights.
This list should also include Charles Stross Laundry Files series.
The concept of high math being a gate to higher dimensions and effectively magic powers provides great setting to a witty and humorous sci-fi prose placed in modern England
It looks like availability of good quality training sets will be a stumbling block for LLM use in Verilog chip design since pretraining with other programming language corpus is not transferable. (see below for quote from Nvidia paper)
A lot of high quality Verilog is locked in licensed, close source IP blocks covered by NDAs.
HDLBits problems are a toy level complexity circuits suitable for Verilog 101 course material.
I would set a benchmark for serious HDL design LLM at reaching ability to implement AXI bus components with specified by user functionality, e.g. AXI4 Slave (address, data widths, burst capability) with memory implemented as banked synchronous SRAM.
* Despite the fact that multi models undergo pretraining on an extensive corpus of multi-lingual code data,
they exhibit only marginal enhancements of approximately
3% when applied to Verilog coding task. This observation
potentially suggests that there is limited positive knowledge transfer between software programming languages like C++ and hardware descriptive languages such as Verilog. This highlights the significance of pretraining on substantial Verilog corpora, as it can significantly enhance model performance in Verilog-related tasks *
https://www.npr.org/2020/10/03/919831116/irish-court-rules-s...