That's a very important point. For instance on Intel's CPUs multiplication is pipelined - its latency is 3 cycles, but throughput is 1 cycle. Thus completing N multiplication takes 2 + N cycles (in the best case), not 3 * N.
Disclaimer: I'm one of the authors of sneller core. We have been working on this project for more than a year. It's has got neat AVX512-centered architecture and many neat tricks inside.
It was already said by the author, that approx ~70% of patches can be applied independently in various part of the source tree. The rest has to be synchronised.
Author here. I cannot use BSR, because have to execute code for all bits, regardless their value. The range is: the last bit to the first with value 1. It's a non-obvious iteration schema. :)
> In continental Europe I have often been in a room with people from 10 different countries say Germany, France, Italy, Russia, Poland, India, China, Korea, England. Everyone could understand each other's broken English with the exception that half of the people couldn't understand English guy.
The problem is that most people are not exposed to real-life English. It's either quite artificial language during classes or well spoken lines in movies. Words are spoken slower and clearer. Native speakers speak fast, use linking, colloquial language, multitude of idioms, phrasal verbs, and tons of stuff never ever touched during classes.