Antenna Diodes in the Pentium Processor(righto.com)
righto.com
Antenna Diodes in the Pentium Processor
http://www.righto.com/2024/11/antenna-diodes-in-pentium-processor.html
53 comments
Author here: I know this is a very obscure topic, but hopefully it will be interesting to some. Let me know if there are any questions...
Absolutely fascinating!
It’s precisely these orthogonal, secondary concerns that make every industry more difficult than people on the outside might think.
Articles like yours shed light on these challenges.
I’m reminded of a recent project working on a (small!) data warehouse where for the first time in my career I had to not only be concerned with theoretical performance of queries, such as the presence or absences of indexes, but orthogonal concerns such as the time taken to rewrite terabytes of data on disk during night ETL jobs… combining with the “change rate” of the source data.
Your article is a similar concern that only specialists in the in the industry are even aware of: it’s not enough to logically route connections — a challenging optimisation all by itself — but there are these competing physical optimisation issues as well that need to be simultaneously optimised!
It’s precisely these orthogonal, secondary concerns that make every industry more difficult than people on the outside might think.
Articles like yours shed light on these challenges.
I’m reminded of a recent project working on a (small!) data warehouse where for the first time in my career I had to not only be concerned with theoretical performance of queries, such as the presence or absences of indexes, but orthogonal concerns such as the time taken to rewrite terabytes of data on disk during night ETL jobs… combining with the “change rate” of the source data.
Your article is a similar concern that only specialists in the in the industry are even aware of: it’s not enough to logically route connections — a challenging optimisation all by itself — but there are these competing physical optimisation issues as well that need to be simultaneously optimised!
Reading through, appears this is mostly a manufacturing concern that goes away once the chip is actually active. Correct? The charge buildup goes away, and then there's no further need for the diode antenna.
However, second question, does any chip actually use these for anything afterward? Or are these ever built so they actually do something other than simple provide manufacturing protection?
Example, they build up charge. So then the charge build up itself is effectively used as some form of remote communication method or channel between various portions of the chip. The diode discharges and in discharging effectively acts as some form of communication transfer.
Others, or it serves multiple purposes. One during manufacturing, one after manufacturing? Safety mechanism during manufacturing, and then the charge buildup location is oscillated, purposely charged, or used as a charge outlet for some other reason?
Others, Light Emitting Diode is, kind of by the name, a diode. Any of these that basically do blinking communication or something similar? Emits light when the charge breaks down, then that is picked up and used as data transfer?
Others, not going into extensively. Tune radio and TV receivers (varactor diodes). Generate radio-frequency oscillations (like actual antennas) (tunnel diodes, Gunn diodes, IMPATT diodes).
Basically, anything other than a safety mechanism for manufacturing?
However, second question, does any chip actually use these for anything afterward? Or are these ever built so they actually do something other than simple provide manufacturing protection?
Example, they build up charge. So then the charge build up itself is effectively used as some form of remote communication method or channel between various portions of the chip. The diode discharges and in discharging effectively acts as some form of communication transfer.
Others, or it serves multiple purposes. One during manufacturing, one after manufacturing? Safety mechanism during manufacturing, and then the charge buildup location is oscillated, purposely charged, or used as a charge outlet for some other reason?
Others, Light Emitting Diode is, kind of by the name, a diode. Any of these that basically do blinking communication or something similar? Emits light when the charge breaks down, then that is picked up and used as data transfer?
Others, not going into extensively. Tune radio and TV receivers (varactor diodes). Generate radio-frequency oscillations (like actual antennas) (tunnel diodes, Gunn diodes, IMPATT diodes).
Basically, anything other than a safety mechanism for manufacturing?
You're correct that these are for manufacturing only. I've never heard of them being used for actual design purposes and that's probably because if you wanted an actual diode, you'd just use a "real" one.
Cool. Thanks for the confirmation answer. Just figured maybe "money efficiency?" Get double functions out of the same wiring path? Or it might do something neat.
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Hi Ken! Your work is extremely interesting to me and I admire the effort your pour into these articles. It's been very cool to see your die analyses ramp up to more and more complex chips over the years. The Pentium is an especially neat target since it represents a major shift in the x86 architecture towards the modern chips we have today. Never a dull moment when I see a righto link!
Your pictures give insight into such a small world, individual freaking transistors on a CPU chip! Reading textbooks and wiki is one thing, but seeing silicon spliced up and photographed up close is another. Very interesting read, and very well presented too, thank you.
It'd be interesting to see how big a CPU chip scaled up to be big enough for a human to fit in (were it hollowed out) would end up being.
Not a whole chip, but an important section of one:
https://www.zerotoasiccourse.com/post/3dcells/
https://www.zerotoasiccourse.com/post/3dcells/
They're usually 150μm thick. Humans fit in about 300mm thick spaces, so you need 2000x linear scale.
Not to answer your question exactly but ...
Chips seem to be around 25mm sq, and the smallest features around 10nm. If you scaled up so the smallest feature is one mm then the chip would be around 2.5km square. (over 1.5 miles on each side)
If the smallest feature was about the width of human hair then divide the above by 100.
Chips seem to be around 25mm sq, and the smallest features around 10nm. If you scaled up so the smallest feature is one mm then the chip would be around 2.5km square. (over 1.5 miles on each side)
If the smallest feature was about the width of human hair then divide the above by 100.
Reminds me of the Monster 6502. Not quite what you're suggesting, but still a large discrete monster of a board.
https://monster6502.com/
Instead of a hedge maze maybe we can have VR "walking through a 8086 or 8088" chip style maze in the future.
https://monster6502.com/
Instead of a hedge maze maybe we can have VR "walking through a 8086 or 8088" chip style maze in the future.
Great article!
> Note that when the chip is completed, every transistor gate is connected to another transistor's source or drain (which provides the signal to the gate)
That's a very curious assertion, which made me think a bit more (it feels incorrect at first but on a second thought it looks correct)
I would think of "pure input pins" but I suppose those have pull-up or pull-down "resistors" which in silicon are actually diodes? gateless fets?
> Note that when the chip is completed, every transistor gate is connected to another transistor's source or drain (which provides the signal to the gate)
That's a very curious assertion, which made me think a bit more (it feels incorrect at first but on a second thought it looks correct)
I would think of "pure input pins" but I suppose those have pull-up or pull-down "resistors" which in silicon are actually diodes? gateless fets?
Late to the show, but this only works because the deposited charge always has the same sign, correct? For instance, if the ions used are positive icons (electrons stripped), the surface elements get positively charged, and the diodes drain that charge to the substrate. But, in operation, the surface elements are negatively charged, so the diodes block. (Right? Or is it the other way around?)
The diodes break down nondestructively under the voltage, getting rid of the charge regardless of polarity. During operation of the chip, the diodes are reverse biased, so they have no effect.
How are vias manufactured, and why tungsten (I suppose it has something to do with high fusion point?).
They etch holes in the oxide for the vias and then use CVD (chemical vapor deposition) to put a tungsten film over the surface, filling the holes. Then they polish off the excess tungsten with CMP (chemical mechanical planarization). I think there's also an adhesion layer of titanium. I think tungsten vias replaced aluminum vias because tungsten with CVD filled vias better than sputtered aluminum. But then copper vias were used because it has better conductivity and better electromigration characteristics.
This is amazing! How did you get the pictures?
I spent a long time with various chemical processes to remove the layers of the chip before discovering that 1500-grit sandpaper works shockingly well. Then I took the pictures with my metallurgical microscope and stitched the images together with a program called Hugin. I wrote a blog post about the process: https://www.righto.com/2015/12/creating-high-resolution-inte...
Are these structures automatically added by most EDA tools?
(If not, why not?)
(If not, why not?)
Yes. Here is the check in the open source EDA tools.
https://openlane2.readthedocs.io/en/latest/reference/step_co...
Fun fact about "antennas" in chip manufacturing: They have nothing to do with actual antennas. Charge can build up on long wires during manufacturing because the chemicals involved are not neutral and have some interactions with exposed wires. That charge needs to go somewhere to protect the rest of the circuits. There's nothing RF about this.
Later technologies (28 nm and below) have extensive design rules around prevention of "antenna" effects.
Later technologies (28 nm and below) have extensive design rules around prevention of "antenna" effects.
I think that’s incorrect. The article and the Wikipedia page on the antenna effect say antenna effects are caused by plasma etching, which uses RF to create the plasma.
It's a bit confusing. The plasma is created by RF, but the RF doesn't cause the antenna effect (nor do "chemicals"). The charged ions and electrons in the plasma are what cause the charge buildup. The wire acts as an antenna in a metaphorical sense, not a literal sense, as I mentioned in Footnote 3.
I'm fascinated by the fact that we study this 31 year old technology and are amazed by the complexity
Indeed! A thought experiment I have some times is to imagine that every machine on the earth was destroyed overnight. We still have mines, people, books. How long would it take to get back to the level of industrialisation and science that would allow us to make (in this case) a 3 million transistor chip?
The vast majority of people have little idea of how much intellectual effort has gone into the current state of technology.
The vast majority of people have little idea of how much intellectual effort has gone into the current state of technology.
Perhaps decades. Perhaps thousands of years. It probably depends upon why those machines were destroyed. Look at World War II. European nations and Japan rebuilt relatively rapidly then rapidly built upon progress made during the war. On the other hand, we have the decline of the Roman Empire. While we may now acknowledge that the dark ages weren't as dark as our 19th century peers thought, the western world lost the will or the imagination to rebuild at large scales (which the semiconductor industry certainly is).
Indeed. A lady at a bar in Portland once inquired what I thought humanity’s most advanced technological achievement was, after a slight pause I said the modern microprocessor. She laughed in my face at the suggestion. But when I pressed her for an answer of her own, she refueled to say, instead would only insist that my answer was ridiculous. Odd lady.
Haha. I suppose it would be: language. Without it, nothing else is possible.
Sure! Another way you might take it is that the pointy stick is the most advanced: it started out before language, and has had considerably more effort put into modernization.
What’s weird is asking the question and just nope-ing out of the resulting conversation.
What’s weird is asking the question and just nope-ing out of the resulting conversation.
I suppose when you answered with a "digital technology" they could have realized you weren't the right person for them. Now that I think about it, it's a great filtering conversation for a date.
I am pretty sure ordinary people will be amazed by this technology even after a thousand years.
While the discussion of IC architecture is doubtlessly interesting, I want to praise this page, and other pages on that site, for the photos of the circuits. Not only they are enlightening, they also have really great, soothing color palettes.
Are the antenna diodes only there to reduce damage during manufacture or is there also impact runtime in an electromagnetic noisy environment?
The antenna diodes are only relevant during manufacturing, when a metal line is connected on one end but not the other. ESD diodes on the other hand protect inputs against electrostatic discharge when the chip is in use.
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There is a tiny amount of extra capacitance on the net because of the reverse-biased junction of the antenna diode, but that's it. These diodes do get taken into account in when determining timing though.
I thought they were there to allow Van Eck phreaking of the processor state
chuckle brings back good memories. I worked at Intel before and during the Pentium era, and I remember how much effort we had to put into fixing our EDA tools to be able to handle these sorts of things.
I hopped onto the Moore's law bus during the 180-nm to 130-nm transition. I hopped back off during the 65 to 45-nm transition, and I'm glad I did. I can't even imagine what EDA tools have to deal with now.
I hopped onto the Moore's law bus during the 180-nm to 130-nm transition. I hopped back off during the 65 to 45-nm transition, and I'm glad I did. I can't even imagine what EDA tools have to deal with now.
Do you have any interesting stories of chip development during that era? What sort of EDA tools did you use?
I could geeze all day, like the geezer I am, with stories about the good old days :-)
In school, your programming exercises are well-defined, small, and can be completed in a few days. First day of my internship with Intel: "Here is a 50,000-line program somebody has been working on for 8 months. But it's too slow, we need to you speed it up by 10x before the summer ends." LMAO. But I figured out how to do even better than that. The routing graph was implemented using pointers from one node to another. But the grid was rectilinear and not very sparse so I could just use a 2d-array to store the graph. Improved memory, improved cache utilization--it ran 2,000 times faster :-) I got a divisional award and so many stock options I was able to buy a house and a brand-new porsche 911 a few years later.
Imagine your job is to solve an NP-hard problem. Like placing the cells on a chip, or routing the chip. The runtime grows exponentially with your problem size....
...and your problem size doubles every two years :-) Every two years, all your data structures, all your algorithms, have to be revamped so that they can handle twice as much data. We used to call it "Even More's Law" :-)
As far as what tools we used, back then Intel mostly used in-house designed tools. They were not very friendly to newbs, they were built for power users. Hard to use, cryptic commands. Hyper customized to Intel's design flows. Could not be used at any other company.
Every year it became harder and harder to compete with outside vendors like Cadence and Synopsis. Eventually, the era of chip companies making their own EDA tools ended. It was fun until it ended.
The best part, though, was it was the 90's. The iron curtain had fallen, we were friends with Russia and the east block :-) Bill Clinton had eliminated the budget deficit, so borrowing costs were very low, and businesses could expand. The whole dot com thing was going on, and everybody was making more money than they could count.
Then...the supreme court puts George W in office. We spent $3 trillion on oil wars, for false reasons, and for which we got nothing in return. Sure did piss off all of our new friends like Russia, though.
Record surpluses went to record deficits. Interest rates rose, and the entire world economy just collapsed in 2008. Which was right around when this year's high-school graduates were born....nobody has seen what the economy should be like for over a generation now.
In school, your programming exercises are well-defined, small, and can be completed in a few days. First day of my internship with Intel: "Here is a 50,000-line program somebody has been working on for 8 months. But it's too slow, we need to you speed it up by 10x before the summer ends." LMAO. But I figured out how to do even better than that. The routing graph was implemented using pointers from one node to another. But the grid was rectilinear and not very sparse so I could just use a 2d-array to store the graph. Improved memory, improved cache utilization--it ran 2,000 times faster :-) I got a divisional award and so many stock options I was able to buy a house and a brand-new porsche 911 a few years later.
Imagine your job is to solve an NP-hard problem. Like placing the cells on a chip, or routing the chip. The runtime grows exponentially with your problem size....
...and your problem size doubles every two years :-) Every two years, all your data structures, all your algorithms, have to be revamped so that they can handle twice as much data. We used to call it "Even More's Law" :-)
As far as what tools we used, back then Intel mostly used in-house designed tools. They were not very friendly to newbs, they were built for power users. Hard to use, cryptic commands. Hyper customized to Intel's design flows. Could not be used at any other company.
Every year it became harder and harder to compete with outside vendors like Cadence and Synopsis. Eventually, the era of chip companies making their own EDA tools ended. It was fun until it ended.
The best part, though, was it was the 90's. The iron curtain had fallen, we were friends with Russia and the east block :-) Bill Clinton had eliminated the budget deficit, so borrowing costs were very low, and businesses could expand. The whole dot com thing was going on, and everybody was making more money than they could count.
Then...the supreme court puts George W in office. We spent $3 trillion on oil wars, for false reasons, and for which we got nothing in return. Sure did piss off all of our new friends like Russia, though.
Record surpluses went to record deficits. Interest rates rose, and the entire world economy just collapsed in 2008. Which was right around when this year's high-school graduates were born....nobody has seen what the economy should be like for over a generation now.
>became harder and harder to compete with outside vendors like Cadence and Synopsis.
Both Synopsys and Cadence exists because of the work Alberto Sangiovanni-Vincentelli and his students at Berkeley did for Intel to enable synthesis and automatic layout of 386. He was co-founder of both :)
Both Synopsys and Cadence exists because of the work Alberto Sangiovanni-Vincentelli and his students at Berkeley did for Intel to enable synthesis and automatic layout of 386. He was co-founder of both :)
Very cool that this would be on the front page after I picked up a Pentium-75 from my local recycler today, it's an SX969. I can hold this chip in my hand and look up to see Ken's die shots. So cool! The ceramic package these Pentiums came in are pretty unique as well - it kind of sounds like setting a piece of glass down when I set the CPU on my desk.
That Pentium is the 80502, so it's almost the same as the one in my article except that it is built with 600 nm technology instead of 800 nm and it has 200,000 more transistors. It's easy to knock the lid off the package with a chisel if you want to see the die inside.
Do we have the technology to automate reading of decapped chips so that we can reconstruct the logic, something like "OCR"? It seems like such a thing would be hard if it has to deal with all these weird details.
It exists, though I don't know of any free or open versions
Now go look at the need for antenna diodes in SOI technology:) with the substrate no longer the safe haven, a lot more oxides can be exposed to large differential voltages during manufacturing.
I'm a physical design engineer that uses software from Cadence and Synopsys to do chip layout of blocks with billions of standard cells. Our flow automatically puts antenna diodes in for all block input pins. Then the tools are usually good enough to breakup internal nets with layer jumping to avoid antennas.
Some of the charge also comes from the CMP process. Modern chips have about 20 layers of metal but there are lots of other via layers in between those and then all the base layers with the actual transistors. You want the wafer to be flat before building the next layer.
https://en.wikipedia.org/wiki/Chemical-mechanical_polishing