1nm Breakthrough: TSMC, MIT and NTU Published on Nature(buzzorange.com)
buzzorange.com
1nm Breakthrough: TSMC, MIT and NTU Published on Nature
https://buzzorange.com/techorange/en/2021/05/18/1nm-tsmc-mit-ntu/
50 comments
Abstract: Advanced beyond-silicon electronic technology requires both channel materials and also ultralow-resistance contacts to be discovered1,2. Atomically thin two-dimensional semiconductors have great potential for realizing high-performance electronic devices1,3. However, owing to metal-induced gap states (MIGS)4,5,6,7, energy barriers at the metal–semiconductor interface—which fundamentally lead to high contact resistance and poor current-delivery capability—have constrained the improvement of two-dimensional semiconductor transistors so far2,8,9. Here we report ohmic contact between semimetallic bismuth and semiconducting monolayer transition metal dichalcogenides (TMDs) where the MIGS are sufficiently suppressed and degenerate states in the TMD are spontaneously formed in contact with bismuth. Through this approach, we achieve zero Schottky barrier height, a contact resistance of 123 ohm micrometres and an on-state current density of 1,135 microamps per micrometre on monolayer MoS2; these two values are, to the best of our knowledge, the lowest and highest yet recorded, respectively. We also demonstrate that excellent ohmic contacts can be formed on various monolayer semiconductors, including MoS2, WS2 and WSe2. Our reported contact resistances are a substantial improvement for two-dimensional semiconductors, and approach the quantum limit. This technology unveils the potential of high-performance monolayer transistors that are on par with state-of-the-art three-dimensional semiconductors, enabling further device downscaling and extending Moore’s law.
That could be very good news in terms of power consumption for a given amount of computing capacity.
Challenging to read things that are auto-translated from Chinese into English.
From what I gather from the article, didn't get the Nature paper yet, the novelty here is a bismuth deposition process that doesn't damage fine structures underneath it.
This is definitely one of the hard problems in semiconductor manufacturing and as stated, it is implied it allows for very fine lines (1 nm) for connecting elements on a chip. If they can do that in a commercial fab it would help with density, if they are really able to reduce connection resistance to "negligible amounts" then that would be really good for power dissipation.
From what I gather from the article, didn't get the Nature paper yet, the novelty here is a bismuth deposition process that doesn't damage fine structures underneath it.
This is definitely one of the hard problems in semiconductor manufacturing and as stated, it is implied it allows for very fine lines (1 nm) for connecting elements on a chip. If they can do that in a commercial fab it would help with density, if they are really able to reduce connection resistance to "negligible amounts" then that would be really good for power dissipation.
Yes, exactly that. I'm much more happy about the potential for power savings than the possibility to further extend the miniaturization, the latter has a lot of other hurdles that need to be overcome than just in-the-lab process size. Spend enough money and you can already have features that small (and much smaller) in the lab, but the power saving potential here is massive.
Improved contact resistance may translate most significantly to speed. The drive strength of a fet is significantly hampered by high output resistance - especially for small gates.
It isn't quite clear why they are developing 2D. Planar fets must leak terribly at these sizes.
It isn't quite clear why they are developing 2D. Planar fets must leak terribly at these sizes.
That "1nm" is complete marketing bullshit, like it always was, for a decade or two.
Silicon lattice step is ~0.5nm, so 1nm is at most 3 atoms. Current technology is definitely not there yet however we're getting closer. Very interested what marketing department will say after 1nm became old news
Silicon lattice step is ~0.5nm, so 1nm is at most 3 atoms. Current technology is definitely not there yet however we're getting closer. Very interested what marketing department will say after 1nm became old news
The term "5 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density, increased speed and reduced power consumption.
It is an industry standard term for describing a process node which is quite different from marketing bullshit.
Not really standard. Intel is one generation "late" for the same process compared to TSMC.
By TSMC standards, Intel's 7nm is a 5nm process and Intel's 10nm is a 7nm process.
So it is not even industry standard marketing bullshit.
By TSMC standards, Intel's 7nm is a 5nm process and Intel's 10nm is a 7nm process.
So it is not even industry standard marketing bullshit.
It's a random number in front of physical measurement, unrelated to anything from reality.
Just because all of the marketing departments choose to participate in this particular bs doesn't mean it's not pure marketing bs. That just means it's industry standard marketing bs.
Just because all of the marketing departments choose to participate in this particular bs doesn't mean it's not pure marketing bs. That just means it's industry standard marketing bs.
No, it isn't random either but it hasn't been associated with a particular physical feature size since 1997.
How Are Process Nodes Defined?
https://www.extremetech.com/computing/296154-how-are-process...
How Are Process Nodes Defined?
https://www.extremetech.com/computing/296154-how-are-process...
Your source seems to disagree with you.
> The numbers that we use to signify each new node are just numbers that companies pick.
> The numbers that we use to signify each new node are just numbers that companies pick.
It's industry standard to blame anything viewed with disdain on the marketing department, if EEVBlog is anything to go by! ('Product/industrial designers' when it's the same sort of thing but he likes it.)
Except it isn't an industry standard term unless you mean the marketing industry. And the standard for them is it means whatever we say it means.
IMO GiB and gigabit are deliberately consumer-confusing terms with an even clearer standard definition.
Same with 4K, prior to it the number was used to describe the height of the screen (480, 720, 1080) but then 4K describes the width which confuses people into thinking it has 4x the resolution of 1080 when it’s really 2160 (double the resolution.)
The challenge there was combining code systems. 4K as a standard had been used for a relatively long time in digital cinema and editing, and I believe the long-dimension standard was chosen based on telecine processes for scanning film for digital editing and effects. Consumer tech wasn't anywhere near those sorts of resolutions for a very long time, and the 480/720/1080 definition was based on TV broadcasts displayed with CRT scanlines. Then consumer display density rose to the point that it became relevant, and 4K was the preexisting professional name for digital displays in that resolution. It's complicated, but I don't think the choice was intended to confuse.
4K is the successor to 2K. It's not deliberately misleading. Every resolution has had several names:
• 480p/480i, SD
• 720p/720i, HD
• 1080p/1080i, full HD, 2K*
• 2160p, ultra HD, 4K*
* actually refers to several resolutions with different aspect ratios, but roughly the same pixel count
• 480p/480i, SD
• 720p/720i, HD
• 1080p/1080i, full HD, 2K*
• 2160p, ultra HD, 4K*
* actually refers to several resolutions with different aspect ratios, but roughly the same pixel count
Double the linear resolution. 4x the pixels.
But 4K is 4x the 1080 / FullHD. It's twice as wide, and twice as tall, it's four 1080 screens glued together.
But definitely there is nothing 4000 about it, it's 3840 by 2160, about 8.3 megapixels.
But definitely there is nothing 4000 about it, it's 3840 by 2160, about 8.3 megapixels.
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Both powers of 1000 and 1024 are common in computing depending on the context (no it is not just a hard drive thing). Surely it is only reasonable that the non-SI quantities get their own prefix to distinguish them from the SI quantities?
I see consumer confusion as based on our ability to guess whether there's going to be a mismatch between communication and understanding, and despite technical correctness. Admittedly that example is pretty marginal, so I added a better one.
I'm confused - the whole point of this paper appears to be reporting a gate composed of a 2D monolayer of atoms as opposed to a 3D bulk deposition. So it seems like it is "there" in the sense you mean?
>Very interested what marketing department will say after 1nm became old news
0.8nm. Something TSMC stated they intend to bring to market by 2030.
Yes it is marketing term. But I thought everyone should know that by now.
0.8nm. Something TSMC stated they intend to bring to market by 2030.
Yes it is marketing term. But I thought everyone should know that by now.
Picometers await.
But past 500 pm, the distance between silicon atoms in the crystal lattice, it will become increasingly harder to ascribe any physical sense to it at all.
But past 500 pm, the distance between silicon atoms in the crystal lattice, it will become increasingly harder to ascribe any physical sense to it at all.
I'm curious if two gens from now we'll see -1nm or 250pm.
we all know this, we see this comment daily.
Labels for production nodes (e.g. "1nm") have diverged from specific physical distances (e.g. gate width) for years now.
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In a LSD trip someone could wonder if our simulation has no idea what the next evolutionary step is.
Similar how music did not change much in the last 20 years
Similar how music did not change much in the last 20 years
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Poor IBM.
It's as if we had only one efficient oil well for the whole world. It's getting a bit hot.
It's as if we had only one efficient oil well for the whole world. It's getting a bit hot.
TSMC's fabrication leadership has never been greater, regardless of the marketing speak they are at the forefront. All the more amazing given for a "renegade province" that has thrived despite continual attempts to economically isolate it by the empire next door.
>continual attempts to economically isolate it by the empire next door.
LOL. China is Taiwan biggest trade partner and source of trade surplus.
And they can get US military hardware and latest semiconductor equipment tools as well.
LOL. China is Taiwan biggest trade partner and source of trade surplus.
And they can get US military hardware and latest semiconductor equipment tools as well.
Please make your substantive points without swipes.
https://news.ycombinator.com/newsguidelines.html
https://news.ycombinator.com/newsguidelines.html
i don't believe in physical limits for computation since beginning of 90ties when i read about 50MHz being the fundamental impossible to surpass limit and few years later i had DX4-133 running at home. Saying that with high appreciation for the grit of the people in the industry who has taken us that far and going to take even farther.
> i don't believe in physical limits for computation
there are limits, we're just not close to them.
https://en.wikipedia.org/wiki/Limits_of_computation
> when i read about 50MHz being the fundamental impossible to surpass limit
yeah i think the problem here is popular press writing
there are limits, we're just not close to them.
https://en.wikipedia.org/wiki/Limits_of_computation
> when i read about 50MHz being the fundamental impossible to surpass limit
yeah i think the problem here is popular press writing
some of those limits are applicable to black holes only in the state of thermodynamic equilibrium. The miniature unstable black holes/singularities produced using quark-gluon lithography may be not a subject to those limits, and miniature wormhole loops through 4th dimension may prove to be an effective workaround for storage limits, etc.
If you have some good points to disprove Heisenberg's rule then it's worth publishing a paper.
If you are talking about quark litography (which does not physically make any sense as af as I can tell), then you are still agreeing with the parent comment, there are limits but we still have a long way.
If you are talking about quark litography (which does not physically make any sense as af as I can tell), then you are still agreeing with the parent comment, there are limits but we still have a long way.
i hope that any of that has any bearing on engineering practice in our lifetimes.
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> beginning of 90ties when i read about 50MHz being the fundamental impossible to surpass limit
Do you remember what magazine that was in?
It's hard to imagine anyone thinking 50MHz was a fundamental limit to circuit design, or computers, in the 90s. I am very curious what their argument was.
The Cray-1 ran 80MHz in the 70s. http://www.openloop.com/education/classes/sjsu_engr/engr_com...
FM is faster than that and it's been around a long time.
https://en.wikipedia.org/wiki/FM_broadcast_band
Do you remember what magazine that was in?
It's hard to imagine anyone thinking 50MHz was a fundamental limit to circuit design, or computers, in the 90s. I am very curious what their argument was.
The Cray-1 ran 80MHz in the 70s. http://www.openloop.com/education/classes/sjsu_engr/engr_com...
FM is faster than that and it's been around a long time.
https://en.wikipedia.org/wiki/FM_broadcast_band
it was in USSR, so there would have been natural delay in the stuff getting printed there, and also it may have been end of 80-ties. My point here isn't about specific numbers and dates, it is that relatively short period between me reading about the limit and experiencing it getting broken left me with big doubts about the limits, and made me thinking about them more as the limits of our world view and less as real physical limits. Similar like "c" happens to be a speed limit only in the fixed spacetime.
> when i read about 50MHz being the fundamental impossible to surpass limit
Where did you read that? As a working EE through the 80s and until today, I never heard that claimed. Maybe someone, somewhere wrote that, but it would have been an extremely fringe opinion. Even at the time I think most people would have received that opinion as a crock of shit.
Where did you read that? As a working EE through the 80s and until today, I never heard that claimed. Maybe someone, somewhere wrote that, but it would have been an extremely fringe opinion. Even at the time I think most people would have received that opinion as a crock of shit.
The 50 MHz limit had to do with spreading a synchronous clock across the longest dimension of a motherboard. By splitting the on-chip and off-chip clocks out we managed to get much higher clockrates (across much shorter distances). It's often the details that matter a lot with such statements and if a metric is presented without context then you can easily stray into territory where such statements are no longer necessarily valid, even though in principle they carry a core of truth.
In practice the only real fundamental limit to how fast you can clock a processor has to do with the gate rise and fall times, which are in turn intimately coupled to how large those gates are (the main factor in determining their capacitance) and the resistance in the charging circuitry for the gate. This is essentially an RLC network where all of the dominant factors are parasitic. What the real practical limits are is as of yet unknown but you always have to keep in mind is that this is tech at the cutting edge and that what is impossible today may very well a breakthrough away from being common.
In practice the only real fundamental limit to how fast you can clock a processor has to do with the gate rise and fall times, which are in turn intimately coupled to how large those gates are (the main factor in determining their capacitance) and the resistance in the charging circuitry for the gate. This is essentially an RLC network where all of the dominant factors are parasitic. What the real practical limits are is as of yet unknown but you always have to keep in mind is that this is tech at the cutting edge and that what is impossible today may very well a breakthrough away from being common.